SED1565 Datasheet, PDF (32/87 Pages) Epson Company – Direct display of RAM data through the display data RAM

SED1565 Series
When multiple SED1565 Series chips are used, the
slave chips must be supplied the display timing signals
(FR, CL, DOF) from the master chip[s].
Table 5 shows the status of the FR, CL, and DOF
signals.
Master (M/S = “H”)
Slave (M/S = “L”)
Table 5
Operating Mode
The internal oscillator circuit is enabled (CLS = “H”)
The internal oscillator circuit is disabled (CLS = “L”)
The internal oscillator circuit is enabled (CLS = “H”)
The internal oscillator circuit is disabled (CLS = “L”)
FR
Output
Output
Input
Input
CL
Output
Input
Input
Input
DOF
Output
Output
Input
Input
The Common Output Status Select
Circuit
In the SED1565 Series chips, the COM output scan
direction can be selected by the common output status
select command. (See Table 6.) Consequently, the
constraints in IC layout at the time of LCD module
assembly can be minimized.
Status
Normal
Reverse
Table 6
COM Scan Direction
SED1565***
SED1566***
SED1567***
SED1568***
SED1569***
COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51
COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0
The Liquid Crystal Driver Circuits
These are a 197-channel (SED1565 Series), a 181-
channel (SED1566 Series) multiplexers 165-channel
(SED1567 Series) and a 185-channel (SED1569 Series)
that generate four voltage levels for driving the liquid
crystal. The combination of the display data, the COM
scan signal, and the FR signal produces the liquid
crystal drive voltage output.
Figure 6 shows examples of the SEG and COM output
wave form.
8–30
EPSON