EPC901 Datasheet, PDF (8/37 Pages) Espros Photonics corp – CCD line sensor 1024x1 pixel

3.5. Timing parameters
Parameter
Description
Min
Typ
Max
Unit
TSTARTUP
Start-up time after applying external supply/supplies
(includes ramp-up of charge pump)
10
ms
TCP_UP
Charge pump power-up time: time from changing the bit CP_PD
from 1 to 0 until chip is operational (internal VDD5V)
5
ms
TWAKE_UP
Wake-up time from Power-Save mode
7
12
µs
f_OSC
Oscillator clock frequency at nominal trim room temperature
22.4
36
48
MHz
value (OSC_TRIM_REG at default value) _{-20°C < TA < 65°C}
18
36
58
MHz
f_{OSC_MAX_TRIM}
Frequency of oscillator clock that can be achieved through trim-
ming ³ at room temperature.
32
MHz
TSU,CONF
Setup time of configuration pins with respect to rising edge of
50
ns
read pulse
TH,CONF
Hold time of configuration pins with respect to rising edge of read
3
pulse
Oscillator
clock cycles
TSHUTTER
Pulse width of SHUTTER signal
5
Oscillator
clock cycles
TFLUSH
Flush period ¹
30
32
Oscillator
clock cycles
TSHIFT
Shift period ¹
24
26
Oscillator
clock cycles
TRD_PULSE
Pulse width of Read Pulse
3
Oscillator
clock cycles
TCDS
CDS operation
37
Oscillator
clock cycles
TSTORE
TRD_CLK
fREAD
D
TH,VIDEO
Duration how long a frame may be stored in the frame-store
10
Period of the read clock
18.5
READ clock rate (the inverse of TRD_CLK) ²
0.1
READ clock duty cycle @ f_READ max
45
Period during which the output of the video amplifier is held sta-
ble after the last read clock edge
ms
10'000
ns
54
MHz
50
55
%
50
µs
TPERIOD,FLUSH
TPULSE,CLR_DATA
Periodicity of the periodic flush operation ⁴
Pulse width on CLR_DATA
100
3
ms
Oscillator
clock cycles
BI2C
I2C transmission rate
400
kbit/s
Notes:
1 _{By measuring the frequency of the internal clock oscillator (see section 9.), the duration of the internal flush and shift periods can be cal-}
culated exactly.
2 _{To achieve the maximum clock frequency, the duty cycle of the read clock has to be 50% with a maximal tolerance of ±5%.}
3 _{The internal oscillator must not be trimmed to a frequency higher than 50MHz.}
4 _{Refer to section 5.6. for more details.}
3.6. Absolute maximum ratings
Description
Power supply voltage (VDD)
Voltage to any Pin
Storage Temperature Range (TS)
Relative humidity
ESD rating
Conditions
-0.3V to +5V
-0.3 to VDD +0.3V
-40°C to +85°C
0 to 95% non-condensing
all pins except VDD7V0 vs. VDD1V8: HBM class 2 ( 2kV to <4kV, JEDEC)
Pin VDD7V0 vs. VDD1V8:
HBM class 1B (500V to <1kV, JEDEC)
Note: Pin VDD7V0 is in the final circuit loaded with 2.2µF low ESR capacitor.
© 2016 ESPROS Photonics Corporation
Characteristics subject to change without notice
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Datasheet_epc901-V5.6
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