EPC901 Datasheet, PDF (34/37 Pages) Espros Photonics corp – CCD line sensor 1024x1 pixel

15. Self-test mode by fill-and-spill
Instead of generating charge in the CCD by photo-electrical conversion, charge can also be generated electrically by the as-called fill-and-
spill circuitry. To use the fill-and-spill circuitry, the IC has to be forced into test mode.
The basic behavior of the IC by the fill-and-spill circuitry is exactly the same as when the IC is illuminated. I.e. also when fill-and-spill is
used, the acquisition is controlled by SHUTTER, the internal flush and shift operation are similar and the signal DATA_RDY is asserted at
the end of the internal shift operation.
If the CCD is stimulated by the fill-and-spill circuitry, the on-chip test controller coordinates the operation of the fill-and-spill circuitry and the
CCD. The following features of fill-and-spill can be controlled:
■ number of electrons that are injected into the CCD per fill-and-spill cycle (pins ANA_TEST_*)
■ number of fill-and-spill cycles per acquisition (register ANA_TEST_CONF)
■ selection of which pixels are stimulated by fill-and-spill (register ANA_TEST_CONF)
The number of electrons that are injected into each pixel of the CCD during each fill-and-spill cycle depends on the voltages VIN and VDC.
The two voltage levels VIN and VDC are provided through the analog test pads ANA_TEST*.
QFILL_SPILL
0
20k
40k
60k
80k
100k
120k
140k
160k
180k
200k
VIN - VDC
<0
0.44
0.60
0.72
0.84
0.95
1.06
1.16
1.27
1.37
1.46
QFILL_SPILL
220k
240k
260k
280k
300k
320k
340k
360k
380k
400k
-
VIN - VDC
1.56
1.65
1.75
1.85
1.95
2.06
2.17
2.27
2.36
2.54
-
The number of fill-and-spill cycles per acquisition can be configured by NUM_FILL_SPILL_CYC in register ANA_TEST_CONF (see Table
32). The duration of one fill-and-spill cycle is TCYC,FILL_SPILL (see Table 31). In order to allow the full fill-and-spill operation to terminate the
complete fill-and-spill operation, SHUTTER has to remain asserted for at least NUM_FILL_SPILL_CYC * TCYC,FILL_SPILL after the end of the
internal flush operation (see Figure 19).
SHUTTER
CCD operation
Flush Fill-and-spill Shift
T_FLUSH
T_SHIFT
DATA_RDY
> NUM_FILL_SPILL_CYC * T_{CYC,FILL_SPILL}
Figure 19: Timing diagram of a fill-and-spill operation of the CCD
Parameter
VIN
VDC
TCYC,FILL_SPILL
Description
Min
Typ
Voltage range of fill_spill_vin_packet_AI
1.5
Voltage range of fill_spill_vdc_AI
2
Duration of one fill-and-spill cycle
175
Table 31: Parameters for the fill-and-spill operation
Max
5
Unit
V
V
ns
Register bits 3 to 6 of ANA_TEST_CONF are used in fill-and-spill test mode to configure into which pixels charge shall be spilled (see Ta-
ble 32).
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Characteristics subject to change without notice
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