E1729E30 Datasheet, PDF (8/33 Pages) Elpida Memory – 1G bits DDR3 SDRAM

EDJ1108DJBG, EDJ1116DJBG
1.4 IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined.
The figure Measurement Setup and Test Load for IDD and IDDQ Measurements shows the setup and test load for IDD
and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3
SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of
the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Note:IDDQ values cannot be directly used to calculate I/O power of the DDR3 SDRAM. They can be used to support
correlation of simulated I/O power to actual I/O power as outlined in correlation from simulated channel I/O
power to actual channel I/O power supported by IDDQ measurement.
For IDD and IDDQ measurements, the following definitions apply:
• L and 0: VIN ≤ VIL(AC)max
• H and 1: VIN ≥ VIH(AC)min
• MID-LEVEL: defined as inputs are VREF = VDDQ / 2
• FLOATING: don't care or floating around VREF.
• Timings used for IDD and IDDQ measurement-loop patterns are provided in Timings used for IDD and IDDQ
Measurement-Loop Patterns table.
• Basic IDD and IDDQ measurement conditions are described in Basic IDD and IDDQ Measurement Conditions
table.
Note:The IDD and IDDQ measurement-loop patterns need to be executed at least one time before actual IDD or
IDDQ measurement is started.
• Detailed IDD and IDDQ measurement-loop patterns are described in IDD0 Measurement-Loop Pattern table
through IDD7 Measurement-Loop Pattern table.
• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting.
RON = RZQ/7 (34Ω in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40Ω in MR1);
RTT_WR = RZQ/2 (120Ω in MR2);
TDQS Feature disabled in MR1
• Define D = {/CS, /RAS, /CAS, /WE} : = {H, L, L, L}
• Define /D = {/CS, /RAS, /CAS, /WE} : = {H, H, H, H}
Data Sheet E1729E30 (Ver. 3.0)
8