E1729E30 Datasheet, PDF (1/33 Pages) Elpida Memory – 1G bits DDR3 SDRAM

COVER
DATA SHEET
1G bits DDR3 SDRAM
EDJ1108DJBG (128M words × 8 bits)
EDJ1116DJBG (64M words × 16 bits)
Specifications
• Density: 1G bits
• Organization
— 16M words × 8 bits × 8 banks (EDJ1108DJBG)
— 8M words × 16 bits × 8 banks (EDJ1116DJBG)
• Package
— 78-ball FBGA (EDJ1108DJBG)
— 96-ball FBGA (EDJ1116DJBG)
— Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD = 1.5V ± 0.075V
• Data rate
— 2133Mbps/1866Mbps/1600Mbps/1333Mbps (max)
• 1KB page size (EDJ1108DJBG)
— Row address: A0 to A13
— Column address: A0 to A9
• 2KB page size (EDJ1116DJBG)
— Row address: A0 to A12
— Column address: A0 to A9
• Eight internal banks for concurrent operation
• Interface: SSTL_15
• Burst length (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
— Sequential (8, 4 with BC)
— Interleave (8, 4 with BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13, 14
• /CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10
• Precharge: auto precharge option for each burst
access
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
— Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
— TC = 0°C to +95°C
Features
• Double-data-rate architecture: two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
— Synchronous ODT
— Dynamic ODT
— Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern
read out
• ZQ calibration for DQ drive and ODT
• /RESET pin for Power-up sequence and reset function
• SRT range:
— Normal/extended
• Programmable Output driver impedance control
• Seamless BL4 access with bank-grouping
— Applied only for DDR3-1333 and 1600
Document. No. E1729E30 (Ver. 3.0)
Date Published August 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2010-2012