E1729E30 Datasheet, PDF (17/33 Pages) Elpida Memory – 1G bits DDR3 SDRAM

EDJ1108DJBG, EDJ1116DJBG
Table 11: IDD4W Measurement-Loop Pattern
CK,
Sub Cycle Com-
A11
A7 A3 A0
/CK
CKE -Loop number mand /CS /RAS /CAS /WE ODT BA*³ -Am A10 -A9 -A6 -A2 Data*²
0
WR 0
1
0
0
1
00
0 0 0 0 00000000
1
D
1
0
0
0
1
00
0 000⎯
2,3
0
4
/D, /D 1
1
1
1
1
0 0 0 000⎯
WR 0
1
0
0
1
00
0 0 F 0 00110011
5
D
1
0
0
0
1
00
0 0 F0 ⎯
6,7
/D, /D 1
1
1
1
1
0 0 0 0 F0 ⎯
Toggling Static H 1
8 to 15 Repeat Sub-Loop 0, but BA= 1
2
16 to 23 Repeat Sub-Loop 0, but BA= 2
3
24 to 31 Repeat Sub-Loop 0, but BA= 3
4
32 to 39 Repeat Sub-Loop 0, but BA= 4
5
40 to 47 Repeat Sub-Loop 0, but BA= 5
6
48 to 55 Repeat Sub-Loop 0, but BA= 6
7
56 to 63 Repeat Sub-Loop 0, but BA= 7
Notes: 1.
2.
3.
4.
DM must be driven low all the time. DQS, /DQS are used according to write commands, otherwise MID-LEVEL.
Burst sequence driven on each DQ signal by write command. Outside burst operation, DQ signals are MID-LEVEL.
BA: BA0 to BA2.
Am: m means Most Significant Bit (MSB) of Row address.
Table 12: IDD5B Measurement-Loop Pattern
CK,
Sub Cycle Com-
A11
A7 A3 A0
/CK
CKE -Loop number mand /CS /RAS /CAS /WE ODT BA*³ -Am A10 -A9 -A6 -A2 Data*²
0
REF 0
0
0
1
0
00
0 000⎯
0
1, 2
D
1
0
0
0
0
00
0 000⎯
3,4
/D, /D 1
1
1
1
0
0 0 0 0 F0 ⎯
5 to 8 Repeat cycles 1...4, but BA= 1
9 to 12 Repeat cycles 1...4, but BA= 2
Toggling Static H
1
13 to 16 Repeat cycles 1...4, but BA= 3
17 to 20 Repeat cycles 1...4, but BA= 4
21 to 24 Repeat cycles 1...4, but BA= 5
25 to 28 Repeat cycles 1...4, but BA= 6
29 to 32 Repeat cycles 1...4, but BA= 7
2
33 to
nRFC − 1
Repeat Sub-Loop 1, until nRFC − 1. Truncate, if necessary.
Notes: 1.
2.
3.
4.
DM must be driven low all the time. DQS, /DQS are MID-LEVEL.
DQ signals are MID-LEVEL.
BA: BA0 to BA2.
Am: m means Most Significant Bit (MSB) of Row address.
Data Sheet E1729E30 (Ver. 3.0)
17