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| E1729E30 Datasheet, PDF (3/33 Pages) Elpida Memory – 1G bits DDR3 SDRAM | |||
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EDJ1108DJBG, EDJ1116DJBG
Pin Configurations
Pin Configurations (Ã8 configuration)
/xxx indicates active low signal.
78-ball FBGA
1
2
3
A
VSS VDD NC
B
VSS VSSQ DQ0
C
VDDQ DQ2 DQS
D
VSSQ DQ6 /DQS
E
VREFDQ VDDQ DQ4
F
NC VSS /RAS
G
ODT VDD /CAS
H
NC
/CS /WE
J
VSS BA0 BA2
K
VDD A3 A0
L
VSS A5 A2
M
VDD A7 A9
N
VSS /RESET A13
7
8
9
NU/(/TDQS) VSS VDD
DM/TDQS VSSQ VDDQ
DQ1 DQ3 VSSQ
VDD VSS VSSQ
DQ7 DQ5 VDDQ
CK VSS NC
/CK VDD CKE
A10(AP) ZQ NC
NC VREFCA VSS
A12(/BC) BA1 VDD
A1 A4 VSS
A11 A6 VDD
NC A8 VSS
(Top view)
Pin name
Function
Pin name
Function
A0 to A13*3
Address inputs
A10(AP): Auto precharge
A12(/BC): Burst chop
/RESET*3
Active low asynchronous reset
BA0 to BA2*3
Bank select
VDD
Supply voltage for internal circuit
DQ0 to DQ7
Data input/output
VSS
Ground for internal circuit
DQS, /DQS
Differential data strobe
VDDQ
Supply voltage for DQ circuit
TDQS, /TDQS
Termination data strobe
VSSQ
Ground for DQ circuit
/CS*3
Chip select
VREFDQ
Reference voltage for DQ
/RAS, /CAS, /WE*3
Command input
VREFCA
Reference voltage for CA
CKE*3
Clock enable
ZQ
Reference pin for ZQ calibration
CK, /CK
Differential clock input
NC*1
No connection
DM
Write data mask
NU*2
Not usable
ODT*3
ODT control
Notes: 1.
2.
3.
Not internally connected with die.
Don't connect. Internally connected.
Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1729E30 (Ver. 3.0)
3
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