HB52F168GB-B Datasheet, PDF (16/19 Pages) Elpida Memory – 128 MB Unbuffered SDRAM Micro DIMM 16-Mword × 64-bit, 133/100 MHz Memory Bus, 1-Bank Module (4 pcs of 16 M × 16 components) PC133/100 SDRAM

HB52F168GB-B, HB52D168GB-B
Relationship Between Frequency and Minimum Latency
HB52F168GB-B/HB52D168GB-B
Parameter
133
100
Frequency (MHz)
CE latency = 3 CE latency = 2
t_CK (ns)
PC100
Symbol Symbol 7.5
10
Active command to column command I_RCD
3
2
(same bank)
Notes
1
Active command to active command
I _RC
9
7
= [I_RAS + I_RP]
(same bank)
1
Active command to precharge command I_RAS
6
5
1
(same bank)
Precharge command to active command I_RP
3
2
1
(same bank)
Write recovery or data-in to precharge I_DPL
Tdpl 2
2
1
command (same bank)
Active command to active command
I _RRD
2
2
1
(different bank)
Self refresh exit time
I _SREX
Tsrx 1
1
2
Last data in to active command
I _APW
Tdal 5
4
= [I_DPL + I_RP]
(Auto precharge, same bank)
Self refresh exit to command input
I _SEC
9
7
= [I_RC]
3
Precharge command to high impedance I_HZP
Troh 3
2
Last data out to active command
I _APR
1
1
(auto precharge) (same bank)
Last data out to precharge
I _EP
(early precharge)
–2
–1
Column command to column command I_CCD
Tccd 1
1
Write command to data in latency
I _WCD
Tdwd 0
0
DQMB to data in
I _DID
Tdqm 0
0
DQMB to data out
I _DOD
Tdqz 2
2
CKE to CK disable
I _CLE
Tcke 1
1
Register set to active command
I _RSA
Tmrd 1
1
S to command disable
I _CDD
0
0
Power down exit to command input
I _PEC
1
1
Notes: 1. I_RCD to I_RRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP]
Data Sheet E0008H10
16