HB52F168GB-B Datasheet, PDF (13/19 Pages) Elpida Memory – 128 MB Unbuffered SDRAM Micro DIMM 16-Mword × 64-bit, 133/100 MHz Memory Bus, 1-Bank Module (4 pcs of 16 M × 16 components) PC133/100 SDRAM

HB52F168GB-B, HB52D168GB-B
AC Characteristics (Ta = 0 to 65˚C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52F168GB-B/HB52D168GB-B
-75
-A6
-B6
Parameter
PC100
Symbol Symbol Min Max Min Max Min
System clock cycle time
(CE latency = 2)
t _CK
Tclk
10 —
10 —
15
(CE latency = 3)
t _CK
Tclk
7.5 —
10 —
10
CK high pulse width
t _CKH
Tch
3
—
3
—
3
(CE latency = 2)
(CE latency = 3)
t _CKH
Tch
2.5 —
3
—
3
CK low pulse width
t _CKL
Tcl
3
—
3
—
3
(CE latency = 2)
(CE latency = 3)
t _CKL
Access time from CK
(CE latency = 2)
t _AC
(CE latency = 3)
t _AC
Data-out hold time
t _OH
(CE latency = 2)
Tcl
2.5 —
3
—
3
Tac
—6
—6
—
Tac
— 5.4
—6
—
Toh
3
—
3
—
3
(CE latency = 3)
t _OH
CK to Data-out low
t _LZ
impedance
Toh
2.7 —
3
—
3
2
—
2
—
2
CK to Data-out high
t _HZ
impedance
(CE latency = 2)
—6
—6
—
(CE latency = 3)
t _HZ
— 5.4
—6
—
Data-in setup time
(CE latency = 2)
t_AS, t_CS, Tsi
2
—
2
—
2
t_DS, t_CES
(CE latency = 3)
t_AS, t_CS, Tsi
1.5 —
2
—
2
t_DS, t_CES
CKE setup time for
t _CESP
Tpde 2
—
2
—
2
power down exit
(CE latency = 2)
(CE latency = 3)
Data-in hold time
(CE latency = 2)
(CE latency = 3)
t _CESP
Tpde 1.5 —
2
—
2
t_AH, t_CH, Thi
1
—
1
—
1
t_DH, t_CEH
t_AH, t_CH, Thi
0.8 —
1
—
1
t_DH, t_CEH
Max
—
—
—
—
—
—
8
6
—
—
—
6
6
—
—
—
—
—
—
Unit Notes
ns 1
ns
ns 1
ns
ns 1
ns
ns 1, 2
ns
ns 1, 2
ns 1, 2
ns 1, 2, 3
ns 1, 4
ns
ns 1, 5, 6
ns
ns 1
ns
ns 1, 5
ns
Data Sheet E0008H10
13