HB52F168GB-B Datasheet, PDF (14/19 Pages) Elpida Memory – 128 MB Unbuffered SDRAM Micro DIMM 16-Mword × 64-bit, 133/100 MHz Memory Bus, 1-Bank Module (4 pcs of 16 M × 16 components) PC133/100 SDRAM

HB52F168GB-B, HB52D168GB-B
HB52F168GB-B/HB52D168GB-B
-75
-A6
-B6
Parameter
PC100
Symbol Symbol Min Max
Min Max
Min Max
Unit Notes
Ref/Active to Ref/Active t_RC
command period
(CE latency = 2)
Trc
70 —
70 —
70 —
ns 1
(CE latency = 3)
t _RC
Active to Precharge
t _RAS
command period
(CE latency = 2)
Trc
Tras
67.5 —
70 —
70 —
ns
50 120000 50 120000 50 120000 ns 1
(CE latency = 3)
t _RAS
Tras 45 120000 50 120000 50 120000 ns
Active command to
t _RCD
Trcd 20 —
20 —
20 —
ns 1
column command
(same bank)
Precharge to active
t _RP
command period
Trp
20 —
20 —
20 —
ns 1
Write recovery or data-in t_DPL
to precharge lead time
(CE latency = 2)
Tdpl 20 —
20 —
20 —
ns 1
(CE latency = 3)
t _DPL
Active (a) to Active (b) t_RRD
command period
(CE latency = 2)
Tdpl 15 —
Trrd
20 —
20 —
20 —
20 —
20 —
ns
ns 1
(CE latency = 3)
Transition time
(rise and fall)
t _RRD
Trrd
15 —
20 —
20 —
ns
t_T
1
5
1
5
15
ns
Refresh period
t _REF
— 64
— 64
— 64
ms
Notes: 1. AC measurement assumes t_T = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C_L = 50 pF.
3. t_LZ (min) defines the time at which the outputs achieves the low impedance state.
4. t_HZ (max) defines the time at which the outputs achieves the high impedance state.
5. t_CES defines CKE setup time to CK rising edge except power down exit command.
Data Sheet E0008H10
14