HB52F168GB-B Datasheet, PDF (11/19 Pages) Elpida Memory – 128 MB Unbuffered SDRAM Micro DIMM 16-Mword × 64-bit, 133/100 MHz Memory Bus, 1-Bank Module (4 pcs of 16 M × 16 components) PC133/100 SDRAM

HB52F168GB-B, HB52D168GB-B
DC Characteristics (Ta = 0 to 65°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52F168GB-B/HB52D168GB-B
-75
-A6/B6
Parameter
Symbol Min Max Min Max Unit Test conditions Notes
Operating current
(CE latency = 2)
I _CC1
—
(CE latency = 3)
I _CC1
—
Standby current in power I_CC2P
—
down
Standby current in power I_CC2PS
—
down (input signal stable)
400 —
460
12
—
8
—
400 mA Burst length = 1 1, 2, 3
t_RC = min
400 mA
12
mA CKE0 = V_IL,
6
t_CK = 12 ns
8
mA CKE0 = V_IL, t_CK = ∞ 7
Standby current in non
power down
I _CC2N
—
Active standby current in I_CC3P
—
power down
Active standby current in I_CC3N
—
non power down
Burst operating current
I _CC4
—
(CE latency = 2)
80
—
16
—
120 —
440 —
80
mA CKE0, S = V_IH,
4
t_CK = 12 ns
16
mA CKE0, S = V_IH,
1, 2, 6
t_CK = 12 ns
120
mA CKE0, S = V_IH,
t_CK = 12 ns
1, 2, 4
440 mA t_CK = min, BL = 4 1, 2, 5
(CE latency = 3)
Refresh current
Self refresh current
Self refresh current
(L-version)
I _CC4
—
580
440 mA
I _CC5
—
880 —
880
mA t_RC = min
3
I _CC6
—
12
—
12
mA V_IH ≥ V_CC – 0.2 V
8
V_IL ≤ 0.2 V
I _CC6
—
8
—
8
mA
Input leakage current
I _LI
Output leakage current
I _LO
–10 10
–10 10
–10 10
–10 10
µA 0 ≤ Vin ≤ V_CC
µA 0 ≤ Vout ≤ V_CC
DQ = disable
Output high voltage
V_OH
2.4
—
2.4
—
V I_OH = –4 mA
Output low voltage
V_OL
—
0.4
—
0.4
V I_OL = 4 mA
Notes: 1. I_CC depends on output load condition when the device is selected. I_CC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
Data Sheet E0008H10
11