E909-05 Datasheet, PDF (47/67 Pages) ELMOS Semiconductor AG – The HALIOS® multi purpose optical sensor is based on an optical bridge which provides a contactless detec-tion of gestures (e.g. movement of a finger).

HALIOS® MULTI-PURPOSE OPTICAL SENSOR WITH HIGH LIGHT IMMUNITY
E909.05
PRELIMINARY INFORMATION AUG 02, 2011
Command word pending in receive fifo, this means the next byte read from the receive fifo is the first
received byte after the slave has been addressed. Depending on the application software this byte could be
interpreted as a command. The interrupt flag is set back by reading a byte from the receive fifo. The master
will force the interface into a wait state until the application software reads one byte from the fifo.
I2C send request (see 6.11.2 List Of All Interrupts)
This flag signalises that the master is requesting a byte but the send fifo is empty. The interrupt flag is set
back by writing a byte to the send fifo. The master will force the interface into a wait state until the application
software writes one byte to the fifo.
If this interrupt is not used for the communication protocol a default routine has to be implemented to clear
the interrupt in case of unintentional appearance of this interrupt (the interrupt can occur under different cir-
cumstances when the slave address is enclosed in a data byte).
C-code example for default routine:
I2C_TXDATA = 0xff;
// fill “send data fifo register” (see above)
// with one byte of data to clear the interrupt
I2C_CTRL |= I2C_CLRTXFIFO; // clear contents of send fifo registers to
// remove previous written 0xff (control reg.)
I2C send fifo low water (see 6.11.2 List Of All Interrupts)
In case the low water mark (defined in control register) is reached or is exceeded the send fifo low water flag
becomes active. The flag is set back by filling to the send fifo.
I2C receive fifo high water (see 6.11.2 List Of All Interrupts)
If the high water mark (defined in control register) is reached or is exceeded the receive fifo high water flag
becomes active. The flag is set back by reading from the receive fifo.
6.10.9 I²C Wake-up Detection
The I²C interface can be used to wake up the ASIC from any system state. In system state “off” the interface
has to be configured to wake the CPU. Therefore the 'wakeup mode enable bit' has to be set (defined in con-
trol register) before setting the ASIC to “off-mode”. It is only possible to set the 'wakeup mode enable bit' if
the I²C Master has closed the communication on the bus, so the application software has to poll the bit
'wakeup mode enable' (defined in status register) after it was set to make sure the bus is in idle state and the
ASIC can be set to “off-mode”. After a new addressing of the slave on the bus the system will wake up from
“off-mode” and the “I2C wakeup event” interrupt is active as long as the 'wakeup mode enable bit' is set back
to zero (defined in control register). While the wake-up process the interface will force the Master into a wait
state by holding the SCL line low. The application software has to clear the 'wakeup mode enable bit' (defined
in control register) to release the SCL line in order to continue the communication.
6.11 Interrupt Control Module
6.11.1 Interrupt Control Module Structure
• interrupt pending bit flipflops (request hold elements) are located inside asserting modules
• interrupt vector support for more simple and faster interrupt entry
• nested interrupt support
• main interrupt enable MIE for easy cli() and sei() implementation
• N is the number of interrupt vectors
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
Data Sheet 47 / 67
QM-No.: 25DS0014E.00