E909-05 Datasheet, PDF (23/67 Pages) ELMOS Semiconductor AG – The HALIOS® multi purpose optical sensor is based on an optical bridge which provides a contactless detec-tion of gestures (e.g. movement of a finger).

HALIOS® MULTI-PURPOSE OPTICAL SENSOR WITH HIGH LIGHT IMMUNITY
E909.05
PRELIMINARY INFORMATION AUG 02, 2011
6 Microcontroller EL16
6.1 Feature List
The CPU incorporates features specifically designed for modern programming techniques such as calculated
branching, table processing and the use of high-level languages such as C. The CPU can address the com-
plete address range without paging.
The CPU features include:
• RISC architecture with 27 instructions and 7 addressing modes.
• Orthogonal architecture with every instruction usable with every
addressing mode
• Full register access including program counter, status registers, and stack pointer
• 16 registers including PC, SP and status register
• non paged 16-Bit address space
• Word and byte addressing and instruction formats.
• Single-cycle register operations.
• interrupt support
• standby and stop mode support
• bus wait support
• debugging support (JTAG interface)
• failsafe architecture
6.2 Debugging
To access the debug structures of the EL16 CPU a 4-wire standard JTAG interface is used. The JTAG inter-
face can be accessed via the GPIO pins 2 to 5 when the TMODE pin is set to one. TMODE pin set to zero
resets all test and debug structures and the ASIC operates in normal mode (see Fehler: Referenz nicht
gefunden Fehler: Referenz nicht gefunden for details).
6.3 CPU Registers
The EL16 contains 16 registers (R0 to R15) including program counter, stack pointer and status register
6.3.1 Program Counter (PC)
The 16-bit program counter (PC/R0) points to the next instruction to be executed. Each instruction uses an
even number of bytes (two, four, or six), and the PC is incremented accordingly. Instruction accesses in the
64-KB address space are performed on word boundaries, and the PC is aligned to even addresses. The PC
can be addressed with all instructions and addressing modes.
6.3.2 Stack Pointer (SP)
The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and inter-
rupts. It uses a pre-decrement, post-increment scheme. In addition, the SP can be used by software with all
instructions and addressing modes. The SP is initialized into RAM by the user, and is aligned to even
addresses.
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
Data Sheet 23 / 67
QM-No.: 25DS0014E.00