DS87C520_1 Datasheet, PDF (7/42 Pages) Dallas Semiconductor – EPROM/ROM High-Speed Micro

DS87C520/DS83C520
The relative time of two instructions might be different in the new architecture than it was previously. For
example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct”
instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of
time. In the DS87C520/DS83C520, the MOVX instruction takes as little as two machine cycles or eight
oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While
both are faster than their original counterparts, they now have different execution times. This is because
the DS87C520/DS83C520 usually uses one instruction cycle for each instruction byte. The user
concerned with precise program timing should examine the timing of each instruction for familiarity with
the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle.
Many instructions require only one cycle, but some require five. In the original architecture, all were one
or two cycles except for MUL and DIV. Refer to the High-Speed Microcontroller User’s Guide for details
and individual instruction timing.
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special features of the DS87C520/DS83C520. This
allows the DS87C520/DS83C520 to have many new features but use the same instruction set as the 8051.
When writing software to use a new feature, an equate statement defines the SFR to an assembler or
comp iler. This is the only change needed to access the new function. The DS87C520/DS83C520
duplicates the SFRs contained in the standard 80C52. Table 2 shows the register addresses and bit
locations. The High-Speed Microcontroller User’s Guide describes all SFRs.
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