DS87C520_1 Datasheet, PDF (20/42 Pages) Dallas Semiconductor – EPROM/ROM High-Speed Micro

DS87C520/DS83C520
Both ports can operate simultaneously but can be at different baud rates or even in different modes. The
second serial port has similar control registers (SCON1 at C0h, SBUF1 at C1h) to the original. The new
serial port can only use Timer 1 for timer generated baud rates.
TIMER RATE CONTROL
There is one important difference between the DS87C520/DS83C520 and 8051 regarding timers. The
original 8051 used 12 clocks per cycle for timers as well as for machine cycles. The
DS87C520/DS83C520 architecture normally uses four clocks per machine cycle. However, in the area of
timers and serial ports, the DS87C520/DS83C520 will default to 12 clocks per cycle on reset. This allows
existing code with real-time dependencies such as baud rates to operate properly.
If an application needs higher speed timers or serial baud rates, the user can select individual timers to run
at the 4-clock rate. The Clock Control register (CKCON;8Eh) determines these timer speeds. When the
relevant CKCON bit is a logic 1, the DS87C520/DS83C520 uses 4 clocks per cycle to generate timer
speeds. When the bit is a 0, the DS87C520/DS83C520 uses 12 clocks for timer speeds. The reset
condition is a 0. CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3
selects Timer 0. Unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the
timer controls are independent.
POWER-FAIL RESET
The DS87C520/DS83C520 uses a precision band-gap voltage reference to decide if V_CC is out of
tolerance. While powering up, the internal monitor circuit maintains a reset state until V_CC rises above the
V_RST level. Once above this level, the monitor enables the crystal oscillator and counts 65536 clocks. It
then exits the reset state. This power-on reset (POR) interval allows time for the oscillator to stabilize.
A system needs no external components to generate a power-related reset. Anytime V_CC drops below
V_RST , as in power failure or a power drop, the monitor will generate and hold a reset. It occurs
automatically, needing no action from the software. Refer to the Electrical Specifications for the exact
value of V_RST .
POWER-FAIL INTERRUPT
The voltage reference that sets a precise reset threshold also generates an optional early warning Power-
Fail Interrupt (PFI). When enabled by software, the processor will vector to program memory address
0033h if V_CC drops below V_PFW . PFI has the highest priority. The PFI enable is in the Watchdog Control
SFR (WDCON-D8h). Setting WDCON.5 to a logic 1 will enable the PFI. Application software can also
read the PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the
interrupt enable and software must manually clear it.
WATCHDOG TIMER
To prevent software from losing control, the DS87C520/DS83C520 includes a programmable Watchdog
Timer. The Watchdog is a free running timer that sets a flag if allowed to reach a preselected time-out. It
can be (re)started by software.
A typical application is to select the flag as a reset source. When the Watchdog times out, it sets its flag
which generates reset. Software must restart the timer before it reaches its time-out or the processor is
reset.
Software can select one of four time-out values. Then, it restarts the timer and enables the reset function.
After enabling the reset function, software must then restart the timer before its expiration or hardware
will reset the CPU. Both the Watchdog Reset Enable and the Watchdog Restart control bits are protected
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