DS87C520_1 Datasheet, PDF (14/42 Pages) Dallas Semiconductor – EPROM/ROM High-Speed Micro

DS87C520/DS83C520
There are three registers containing bits that are concerned with PMM functions. They are Power
Management Register (PMR; C4h), Status (STATUS; C5h), and External Interrupt Flag (EXIF; 91h).
Clock Divider
Software can select the instruction cycle rate by selecting bits CD1 (PMR.7) and CD0 (PMR.6) as
follows:
CD1
CD0
Cycle rate
0
0
Reserved
0
1
4 clocks (default)
1
0
64 clocks
1
1
1024 clocks
The selection of instruction cycle rate will take effect after a delay of one instruction cycle. Note that the
clock divider choice applies to all functions including timers. Since baud rates are altered, it will be
difficult to conduct serial communication while in PMM. There are minor restrictions on accessing the
clock selection bits. The processor must be running in a 4-clock state to select either 64 (PMM1) or 1024
(PMM2) clocks. This means software cannot go directly from PMM1 to PMM2 or visa versa. It must
return to a 4-clock rate first.
Switchback
To return to a 4-clock rate from PMM, software can simply select the CD1 and CD0 clock control bits to
the 4 clocks per cycle state. However, the DS87C520/DS83C520 provides several hardware alternatives
for automatic Switchback. If Switchback is enabled, then the device will automatically return to a 4-clock
per cycle speed when an interrupt occurs from an enabled, valid external interrupt source. A Switchback
will also occur when a UART detects the beginning of a serial start bit if the serial receiver is enabled
(REN=1). Note the beginning of a start bit does not generate an interrupt; this occurs on reception of a
complete serial word. The automatic Switchback on detection of a start bit allows hardware to correct
baud rates in time for a proper serial reception. A switchback will also occur when a byte is written to
SBUF0 or SBUF1 for transmission.
Switchback is enabled by setting the SWB bit (PMR.5) to a 1 in software. For an external interrupt,
Switchback will occur only if the interrupt source could really generate the interrupt. For example, if
INT0 is enabled but has a low priority setting, then Switchback will not occur on INT0 if the CPU is
servicing a high priority interrupt.
Status
Information in the Status register assists decisions about switching into PMM. This register contains
information about the level of active interrupts and the activity on the serial ports.
The DS87C520/DS83C520 supports three levels of interrupt priority. These levels are Power- fail, High,
and Low. Bits STATUS.7-5 indicate the service status of each level. If PIP (Power- fail Interrupt Priority;
STATUS. 7) is a 1, then the processor is servicing this level. If either HIP (High Interrupt Priority;
STATUS.6) or LIP (Low Interrupt Priority; STATUS.5) is high, then the corresponding level is in
service.
Software should not rely on a lower priority level interrupt source to remove PMM (Switchback) when a
higher level is in service. Check the current priority service level before entering PMM. If the current
service level locks out a desired Switchback source, then it would be advisable to wait until this condition
clears before entering PMM.
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