DS87C520_1 Datasheet, PDF (11/42 Pages) Dallas Semiconductor – EPROM/ROM High-Speed Micro

DS87C520/DS83C520
DATA MEMORY ACCESS CONTROL Table 3
DME1
DME0
DATA MEMEORY ADDRESS
MEMORY FUNCTION
0
0
0000h-FFFFh
External Data Memory *Default condition
0
1
0000h-03FFh
Internal SRAM Data Memory
0400h-FFFFh
External Data Memory
1
0
Reserved
Reserved
1
1
0000h-03FFh
Internal SRAM Data Memory
0400h-FFFBh
Reserved - no external access
FFFCh
Read access to the status of lock bits
FFFDh-FFFFh
Reserved - no external access
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2-0 reflect the programmed status of
the security lock bits LB2-LB0. They are individually set to a logic 1 to correspond to a security lock bit
that has been programmed. These status bits allow software to verify that the part has been locked before
running if desired. The bits are read only.
Note: After internal MOVX SRAM has been initialized, changing DME0/1 bits will have no effect on the
contents of the SRAM.
STRETCH MEMORY CYCLE
The DS87C520/DS83C520 allows software to adjust the speed of off-chip data memory access. The
microcontroller is capable of performing the MOVX in as few as two instruction cycles. The on-chip
SRAM uses this speed and any MOVX instruction directed internally uses two cycles. However, the time
can be stretched for interface to external devices. This allows access to both fast memory and slow
memory or peripherals with no glue logic. Even in high-speed systems, it may not be necessary or
desirable to perform off- chip data memory access at full speed. In addition, there are a variety of memory
mapped peripherals such as LCDs or UARTs that are slow.
The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
It allows the user to select a Stretch value between 0 and 7. A Stretch of 0 will result in a two- machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.
On reset, the Stretch value will default to a 1, resulting in a three-cycle MOVX for any external access.
Therefore, off-chip RAM access is not at full speed. This is a convenience to existing designs that may
not have fast RAM in place. Internal SRAM access is always at full speed regardless of the Stretch
setting. When desiring maximum speed, software should select a Stretch value of 0. When using very
slow RAM or peripherals, select a larger Stretch value. Note that this affects data memory only and the
only way to slow program memory (ROM) access is to use a slower crystal.
Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. Also, setup and hold times are increased by 1 clock when using any Stretch greater than 0.
This results in a wider read/write strobe and relaxed interface timing, allowing more time for
memory/peripherals to respond. The timing of the variable speed MOVX is in the Electrical
Specifications. Table 4 shows the resulting strobe widths for each Stretch value. The memory Stretch
uses the Clock Control Special Function Register at SFR location 8Eh. The Stretch value is selected using
bits CKCON.2-0. In the table, these bits are referred to as M2 through M0. The first Stretch (default)
allows the use of common 120 ns RAMs without dramatically lengthening the memory access.
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