CY8C20X34_08 Datasheet, PDF (99/216 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

I2C Slave
When clocking the input with a frequency other than 6/12
MHz (for example, clocking the PSOC device with an exter-
nal clock), the baud rates and sampling rates will scale
accordingly. Whether the block works in a Standard Mode or
Fast Mode system depends upon the sample rate. The sam-
ple rate must be sufficient to resolve bus events, such as
Start and Stop conditions. (See the Philips Semiconductors’
I²C™ Specification, version 2.1, for minimum Start and Stop
hold times.)
Bit 0: Enable. When the slave is enabled, the block gener-
ates an interrupt on any Start condition and an address byte
that it receives indicating the beginning of an I2C transfer.
The block is clocked from an external master. Therefore, the
block works at any frequency up to the maximum defined by
the currently selected clock rate. The internal clock is only
used to ensure that there is adequate setup time from data
output to the next clock on the release of a slave stall. When
the Enable bit is ‘0’, the block is held in reset and all status is
cleared. Block enable will be synchronized to the SYSCLK
clock input (see “Timing Diagrams” on page 101).
Enable
No
Yes
Block Operation
Disabled
The block is disconnected from the GPIO pins, P1[5] and P1[7].
(The pins may be used as general purpose IO.) When the slave
is enabled, the GPIO pins are under control of the I2C hardware
and are unavailable.
All internal registers (except I2C_CFG) are held in reset.
Slave Mode
Any external Start condition will cause the block to start receiving
an address byte. Regardless of the current state, any Start resets
the interface and initiates a Receive operation. Any Stop will
cause the block to revert to an idle state
For additional information, refer to the I2C_CFG register on
page 167.
14.3.2 I2C_SCR Register
Address
Name
0,D7h
I2C_SCR
LEGEND
# Access is bit specific.
Bit 7
Bus Error
Bit 6
Bit 5
Stop
Status
Bit 4
ACK
Bit 3
Address
Bit 2
Transmit
Bit 1
LRB
Bit 0
Byte
Complete
Access
# : 00
The I2C Status and Control Register (I2C_SCR) is used by
the slave to control the flow of data bytes and to keep track
of the bus state during a transfer.
This register contains status bits, for determining the state of
the current I2C transfer, and control bits, for determining the
actions for the next byte transfer. At the end of each byte
transfer, the I2C hardware interrupts the M8C microcontrol-
ler and stalls the I2C bus on the subsequent low of the
clock, until the PSoC device intervenes with the next com-
mand. This register may be read as many times as neces-
sary; but on a subsequent write to this register, the bus stall
is released and the current transfer will continue.
There are six status bits: Byte Complete, LRB, Address,
Stop Status, Lost Arb, and Bus Error. These bits have Read/
Clear (RC) access, which means that they are set by hard-
ware but may be cleared by a write of ‘0’ to the bit position.
Under certain conditions, status is cleared automatically by
the hardware. These cases are noted in the table shown
below.
There are two control bits: Transmit and ACK. These bits
have RW access and may be cleared by hardware.
Bit 7: Bus Error. The Bus Error status detects misplaced
Start or Stop conditions on the bus. These may be due to
noise, rogue devices, or other devices that are not yet syn-
chronized with the I2C bus traffic. According to the I2C
specification, all compatible devices must reset their inter-
face on a received Start or Stop. This is a natural thing to do
in Slave mode because a Start will initiate an address recep-
tion and a Stop will idle the slave.
A bus error is defined as follows. A Start is only valid if the
block is idle or a Slave receiver is ready to receive the first
bit of a new byte after an ACK. Any other timing for a Start
condition causes the Bus Error bit to be set. A Stop is only
valid if the block is idle or a Slave receiver is ready to
receive the first bit of a new byte after an ACK. Any other
timing for a Stop condition causes the Bus Error bit to be set.
Spec. # 001-13033 Rev. *A, February 19, 2008
99
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