CY8C20X34_08 Datasheet, PDF (93/216 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

Digital Clocks
13.2.2 OSC_CR0 Register
Address
Name
1,E0h
OSC_CR0
Bit 7
Bit 6
Disable Buzz
Bit 5
No Buzz
Bit 4
Bit 3
Sleep[1:0]
Bit 2
Bit 1
CPU Speed[2:0]
Bit 0
Access
RW : 01
The Oscillator Control Register 0 (OSC_CR0) is used to
configure various features of internal clock sources and
clock nets.
Bit 6: Disable Buzz. Setting this bit causes the bandgap
and POR/LVD systems to remain powered off continuously
during sleep. In this case, there is no periodic “buzz” (brief
wakeup) of these functions during sleep. This bit has no
effect when the No Buzz bit is set high.
Bit 5: No Buzz. Normally, when the Sleep bit is set in the
CPU_SCR register, all PSoC device systems are powered
down, including the bandgap reference. However, to facili-
tate the detection of POR and LVD events at a rate higher
than the sleep interval, the bandgap circuit is powered up
periodically (for about 60 μs) at the Sleep System Duty
Cycle, which is independent of the sleep interval and typi-
cally higher. When the No Buzz bit is set, the Sleep System
Duty Cycle value is overridden and the bandgap circuit is
forced to be on during sleep. This results in faster response
to an LVD or POR event (continuous detection as opposed
to periodic), at the expense of higher average sleep current.
Bits 4 and 3: Sleep[1:0]. The available sleep interval
selections are shown in the table below. Sleep intervals are
approximate based on the accuracy of the internal low
speed oscillator.
Sleep Interval Sleep Timer
OSC_CR[4:3]
Clocks
00b (default)
01b
10b
11b
64
512
4096
32,768
Sleep Period
(nominal)
1.95 ms
15.6 ms
125 ms
1 sec
Watchdog
Period
(nominal)
6 ms
47 ms
375 ms
3 sec
The CPU frequency is changed with a write to the
OSC_CR0 register. There are eight frequencies generated
from a power-of-two divide circuit which are selected by a 3-
bit code. At any given time, the CPU 8-to-1 clock mux is
selecting one of the available frequencies, which is resyn-
chronized to the 12 MHz master clock at the output.
A slow IMO option is also supported, as discussed in the
IMO chapter in the “Architectural Description” on page 57.
This offers an option to lower both system and CPU clock
speed in order to save power.
Bits
000b
001b
010b
011b
100b
101b
110b
111b
6 MHz Internal
Main Oscillator
750 kHz
1.5 MHz
3 MHz
6 MHz
375 kHz
187.5 kHz
46.8 kHz
23.4 kHz
12 MHz Internal
Main Oscillator
1.5 MHz
3.0 MHz
6.0 MHz
12.0 MHz
750 kHz
375 kHz
93.7 kHz
46.8 kHz
External Clock
EXTCLK/ 8
EXTCLK/ 4
EXTCLK/ 2
EXTCLK/ 1
EXTCLK/ 16
EXTCLK/ 32
EXTCLK/ 128
EXTCLK/ 256
An automatic protection mechanism is available for systems
that need to run at peak CPU clock speed but cannot guar-
antee a high enough supply voltage for that clock speed.
See the LVDTBEN bit in the “VLT_CR Register” on page 113
for more information.
For additional information, refer to the OSC_CR0 register on
page 186.
Bits 2 to 0: CPU Speed[2:0]. The PSoC M8C may operate
over a range of CPU clock speeds as illustrated in the table
below, allowing the M8C’s performance and power require-
ments to be tailored to the application.
The reset value for the CPU speed bits is 001b. Therefore,
the default CPU speed is one fourth of the clock source. The
internal main oscillator is the default clock source for the
CPU speed circuit; therefore, the default CPU speed is 3.0
MHz. See “External Clock” on page 90 for more information
on the supported frequencies for externally supplied clocks.
Spec. # 001-13033 Rev. *A, February 19, 2008
93
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