CY8C20X34_08 Datasheet, PDF (74/216 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

CapSense Module
10.2 Register Definitions
The following registers are associated with the CapSense Module and are listed in address order. The register descriptions
have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are
reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0’. For a
complete table of CapSense Module registers, refer to the “Summary Table of the CapSense Registers” on page 70.
10.2.1 CS_CR0 Register
Address
Name
0,A0h
CS_CR0
Bit 7
Bit 6
CSOUT[1:0]
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
MODE[1:0]
Bit 0
EN
Access
RW : 00
The CapSense Control Register 0 (CS_CR0) controls the
operation of the CapSense counters. Bits [7:1] should never
be written to while the block is enabled.
Bits 7 and 6: CSOUT[1:0]. These bits select between a
number of CapSense signals that can be driven to an output
pin. Refer to Figure 10-3 on page 72 for the COL and COH,
and to Figure 10-7 on page 79 for IN and CS_INT.
CSOUT[1:0]
00
01
10
11
IN
CS_INT
COL
COH
Description
Bits 2 and 1: MODE[1:0]. These bits specify the operating
mode of the counter logic. The modes are shown in this
table.
MODE[1:0]
00
01
10
11
Description
Stop On Event
In this mode, the block starts counting when the EN bit is
set, and stops counting on the selected interrupt event. This
mode allows the user to read the counter results in firm-
ware. Counting can be started again by disabling and re-
enabling the block using the EN bit.
Pulse Width
In this mode, after the EN bit is set, the block waits for a
positive edge on the data input selection to start the
counter, and then stops the counter on the following nega-
tive edge of the data input. Polarity can be adjusted with the
INV bit (CS_CR1). Counting can be started again by dis-
abling and re-enabling the block using the EN bit.
Period
In this mode, after the EN bit is set, the block waits for a
positive edge on the data input selection to start the
counter, and then stops the counter on the following posi-
tive edge of the data input. Polarity can be adjusted with the
INV bit (CS_CR1). Counting can be started again by dis-
abling and re-enabling the block using the EN bit.
Continuous
In this mode, the counter can be used to generate a peri-
odic interrupt. The period is set by the input clock selection
in conjunction with using one 8-bit counter (period=100h) or
the chained 16-bit counter (period = 10000h).
Bit 0: EN. When this bit is written to ‘1’, the counters are
enabled for counting. When this bit is written to ‘0’, counting
is stopped and all counter values are reset to ‘0’. If the
counting mode is stopped in conjunction with an event (see
MODE[1:0]), the current count is held and can be subse-
quently read from the counter registers. The EN bit must be
toggled to ‘0’ and then back to ‘1’ to start a new count.
For additional information, refer to the CS_CR0 register on
page 150.
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Spec. # 001-13033 Rev. *A, February 19, 2008
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