CY8C20X34_08 Datasheet, PDF (165/216 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

20.3.27 MVR_PP
MVI Read Page Pointer Register
MVR_PP
0,D4h
Individual Register Names and Addresses:
MVR_PP: 0,D4h
0,D4h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
Bit Name
Page Bit
This register sets the effective SRAM page for MVI read memory accesses in a multi-SRAM page PSoC device.
This register is only used when a device has more than one page of SRAM.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the Register Definitions on page 34 in the
RAM Paging chapter.
Bit
Name
0
Page Bit
Description
This bit determines on which SRAM page an MVI Read instruction operates.
0b
SRAM Page 0
1b
SRAM Page 1
Note A value beyond the available SRAM, for a specific PSoC device, is not set.
Spec. # 001-13033 Rev. *A, February 19, 2008
165
[+] Feedback