CY8C20X34_08 Datasheet, PDF (131/216 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

Programmable Timer
19.2 Register Definitions
The following registers are associated with the Programmable Timer and are listed in address order. The register descriptions
have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are
reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0’. For a
complete table of programmable timer registers, refer to the “Summary Table of the System Resource Registers” on page 88.
19.2.1 PT_CFG Register
Address
Name
0,B0h
PT_CFG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
One Shot
Bit 0
START
Access
RW : 00
The Programmable Timer Configuration Register (PT_CFG)
configures the PSoC’s programmable timer.
Bit 1: One Shot. This bit determines if the timer runs in one
shot mode or continuous mode. In one-shot mode the timer
completes one full count cycle and terminates. Upon termi-
nation, the START bit in this register is cleared. In continu-
ous mode, the timer reloads the count value each time upon
completion of its count cycle and repeats.
Bit 0: START. This bit starts the timer counting from a full
count. The full count is determined by the value loaded into
the DATA registers. This bit is cleared when the timer is run-
ning in one shot mode upon completion of a full count cycle.
For additional information, refer to the PT_CFG register on
page 159.
19.2.2 PT_DATA1 Register
Address
Name
0,B1h
PT_DATA1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Data[4:0]
Bit 1
Bit 0
Access
RW : 00
The Programmable Timer Data Register 1 (PT_DATA1)
holds the upper 5 bits of the progammable timer’s count
value.
Bits 4 to 0: Data[4:0]. These bits hold the upper 5 bits of
the timer’s 13-bit count value.
For additional information, refer to the PT_DATA1 register
on page 160.
19.2.3 PT_DATA0 Register
Address
Name
0,B2h
PT_DATA0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Data[7:0]
Bit 2
Bit 1
Bit 0
Access
RW : 00
The Programmable Timer Data Register 0 (PT_DATA0)
holds the lower 8 bits of the progammable timer’s count
value.
Bits 7 to 0: Data[7:0]. These bits hold the lower 8 bits of
the timer’s13-bit count value.
For additional information, refer to the PT_DATA0 register
on page 161.
Spec. # 001-13033 Rev. *A, February 19, 2008
131
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