CY8C20X34_08 Datasheet, PDF (54/216 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

General Purpose IO (GPIO)
6.1.5.1 Interrupt Modes
GPIO interrupts use the IOINT bit from the IO_CFG register.
The setting of IOINT determines the interrupt mode for all
GPIO.
Interrupt mode IOINT=0 means that the block will assert the
GPIO interrupt line (INTO) when the pin voltage is low, pro-
viding the block’s bit interrupt enable line is set (high).
Interrupt mode IOINT=1 means that the block will assert the
interrupt line (INTO) when the pin voltage is the opposite of
the last state read from the pin, providing the block’s bit
interrupt enable line is set high. This mode switches
between low mode and high mode, depending on the last
value that was read from the port during reads of the data
register (PRTxDR). If the last value read from the GPIO was
‘0’, the GPIO pin will subsequently be in Interrupt High
mode. If the last value read from the GPIO was ‘1’, the GPIO
will then be in Interrupt Low mode.
Table 6-1. GPIO Interrupt Modes
IE
IOINT
Description
0
0
Bit interrupt disabled, INTO de-asserted
0
1
Bit interrupt disabled, INTO de-asserted
1
0
Assert INTO when PIN = low
1
1
Assert INTO when PIN = change from last read
Figure 6-3 assumes that the GIE is set, GPIO interrupt mask
is set, and that the IOINT bit has been set to high. The
Change Interrupt mode relies on the value of an internal
read register to determine if the pin state has changed.
Therefore, the port that contains the GPIO in question must
be read during every interrupt service routine. If the port is
not read, the Interrupt mode will act as if it is in high mode
when the latch value is ‘0’ and low mode when the latch
value is ‘1’.
Figure 6-3. GPIO Interrupt Mode IOINT = 1
Last Value Read From Pin was ‘0’
Pin State Waveform
(a)
Pin State Waveform
(b)
GPIO pin
interrupt
enable set
Interrupt
occurs
GPIO pin
interrupt
enable set
Interrupt
occurs
Last Value Read From Pin was ‘1’
Pin State Waveform
(c)
Pin State Waveform
(d)
GPIO pin
interrupt
enable set
Interrupt
occurs
GPIO pin
interrupt
enable set
Interrupt
occurs
6.1.6 Data Bypass
GPIO pins can be configured to either output data through
CPU writes to the PRTxDR registers, or to bypass the port's
data register and output data from internal functions instead.
The bypass path is shown in Figure 6-1 by the Alt Data
input, which is selected by the Alt Select input. These data
bypass options are selected in one of two ways.
For internal functions such as I2C and SPI, the hardware
automatically selects the bypass mode for the required pins
when the function is enabled. In addition, some bypass out-
puts are selected by the user through the OUT_P1 register.
For these, the pin is configured for data bypass when the
register bit is set high, which allows an internal signal to be
driven to the pin.
For all bypass modes, the desired drive mode of the pin
must be configured separately for each pin, with the
PRTxDM1 and PRTxDM0 registers.
54
Spec. # 001-13033 Rev. *A, February 19, 2008
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