CY8C20X34_08 Datasheet, PDF (150/216 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

CS_CR0
0,A0h
20.3.12 CS_CR0
CapSense Control Register 0
Individual Register Names and Addresses:
CS_CR0 : 0,A0h
0,A0h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
Bit Name
CSOUT[1:0]
MODE[1:0]
EN
This register controls the operation of the CapSense counters.
Never write to bits [7:1] while the block is enabled.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the Register Definitions on page 74 in the
CapSense Module chapter.
Bit
Name
7:6
CSOUT[1:0]
2:1
MODE[1:0]
0
EN
Description
CapSense Output
00b Selected Input
01b CapSense Interrupt
10b Carry Out Low Byte
11b Carry Out High Byte
CapSense Counter Mode
00b Event mode. Start in Enable, stop on interrupt event.
01b Pulse Width mode. Start on positive edge of next input. Stop on negative edge of input.
10b Period mode. Start on positive edge of input. Stop on next positive edge of input.
11b Start in Enable, continuous operation until disable.
0
Counting is stopped and all counter values are reset to ‘0’.
1
Counters are enabled for counting.
150
Spec. # 001-13033 Rev. *A, February 19, 2008
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