CY8C20X34_08 Datasheet, PDF (70/216 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

Section C: CapSense System
CapSense Register Summary
This table lists all the PSoC registers for the CapSense system in address order within their system resource configuration.
The bits that are grayed out are reserved bits. If these bits are written, always write them with a value of ‘0’.
Summary Table of the CapSense Registers
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CAPSENSE MODULE REGISTERS (page 71)
0,A0h
0,A1h
0,A2h
0,A3h
0,A4h
0,A5h
0,A6h
0,A7h
0,A8h
0,FDh
CS_CR0
CS_CR1
CS_CR2
CS_CR3
CS_CNTL
CS_CNTH
CS_STAT
CS_TIMER
CS_SLEW
IDAC_D
CSOUT[1:0]
MODE[1:0]
EN
CHAIN
CLKSEL[1:0]
RLOSEL
INV
INSEL[2:0]
IRANGE[1:0]
IDACDIR IDAC_EN
PXD_EN
RO_EN
IBOOST REFMUX REFMODE REF_EN
LPFilt[1:0]
LPF_EN[1:0]
Data[7:0]
Data[7:0]
INS
COLS
COHS
PPS
INM
COLM
COHM
PPM
Timer Count Value[5:0]
FastSlew[6:0]
FS_EN
IDACDATA[7:0]
IO ANALOG MULTIPLEXER REGISTERS (page 81)
0,61h
1,D8h
1,D9h
1,DAh
1,DBh
AMUX_CFG
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
ICAPEN[1:0]
ENABLE[7:0]
ENABLE[7:0]
ENABLE[7:0]
ENABLE[7:0]
INTCAP[1:0]
COMPARATOR REGISTERS (page 83)
0,78h
0,79h
0,7Ah
0,7Bh
0,7Ch
CMP_RDC
CMP_MUX
CMP_CR0
CMP_CR1
CMP_LUT
CMP1D
CMP0D
INP1[1:0]
INN1[1:0]
CMP1R
CMP1EN
CINT1
CPIN1
CRST1
CDS1
LUT1[3:0]
CMP1L
CMP0L
INP0[1:0]
INN0[1:0]
CMP0R
CMP0EN
CINT0
CPIN0
CRST0
CDS0
LUT0[3:0]
Access
RW : 00
RW : 00
RW : 00
RW : 00
R : 00
R : 00
# : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
# : 00
RW : 00
RW : 00
RW : 00
RW : 00
LEGEND
# Access is bit specific. Refer to the Register Reference chapter on page 137 for additional information.
R Read register or bit(s).
W Write register or bit(s).
70
Spec. # 001-13033 Rev. *A, February 19, 2008
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