S6E2H Datasheet, PDF (90/163 Pages) Cypress Semiconductor – 32-bit ARM ® Cortex ® -M4F FM4 Microcontroller

S6E2H Series
Separate Bus Access Asynchronous SRAM Mode
Parameter
MOEX
Minimum pulse width
MCSX↓→Address output
delay time
MOEX↑→Address hold time
MCSX↓→
MOEX↓ delay time
MOEX↑→
MCSX↑ time
MCSX↓→MDQM↓
delay time
Data set up→MOEX↑ time
MOEX↑→
Data hold time
MWEX
Minimum pulse width
MWEX↑→Address output
delay time
MCSX↓→MWEX↓ delay time
Symbol
tOEW
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
tDH - OE
tWEW
tWEH - AX
tCSL - WEL
MWEX↑→MCSX↑ delay time tWEH - CSH
MCSX↓→MDQM↓ delay time
MWEX↓→
Data output time
MWEX↑→
Data hold time
tCSL-WDQML
tCSL-DX
tWEH - DX
Pin Name
MOEX
MCSX[7:0],
MAD[24:0]
MOEX,
MAD[24:0]
MOEX,
MCSX[7:0]
MCSX,
MDQM[1:0]
MOEX,
MADATA[15:0]
MOEX,
MADATA[15:0]
MWEX
MWEX,
MAD[24:0]
MWEX,
MCSX[7:0]
MCSX,
MDQM[1:0]
MCSX,
MADATA[15:0]
MWEX,
MADATA[15:0]
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Min
Max
Unit
MCLK×n-3
-
ns
-9
-12
+9
+12
ns
0
MCLK×m+9
MCLK×m+12
ns
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
ns
0
MCLK×m+9
MCLK×m+12
ns
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
ns
20
38
-
-
ns
0
-
ns
MCLK×n-3
-
ns
0
MCLK×m+9
MCLK×m+12
ns
MCLK×n-9
MCLK×n-12
MCLK×n+9
MCLK×n+12
ns
0
MCLK×m+9
MCLK×m+12
ns
MCLK×n-9
MCLK×n-12
MCLK×n+9
MCLK×n+12
ns
MCLK-9
MCLK-12
MCLK+9
MCLK+12
ns
0
MCLK×m+9
MCLK×m+12
ns
Note:
− When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
Document Number: 001-98943 Rev *C
Page 90 of 163