S6E2H Datasheet, PDF (138/163 Pages) Cypress Semiconductor – 32-bit ARM ® Cortex ® -M4F FM4 Microcontroller

S6E2H Series
13.4.14 I²C Timing
Standard-mode，Fast-mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol Conditions
SCL clock frequency
(Repeated) Start condition
hold time
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
(Repeated) Start condition
setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
Stop condition and
Start condition
Noise filter
fSCL
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUF
tSP
CL = 30 pF,
R = (Vp/IOL)*¹
2 MHz ≤
tCYCP<40 MHz
40 MHz ≤
tCYCP<60 MHz
60 MHz ≤
tCYCP<80 MHz
80 MHz ≤
tCYCP<100 MHz
100 MHz ≤
tCYCP<120 MHz
120 MHz ≤
tCYCP<140 MHz
140 MHz ≤
tCYCP<160 MHz
160 MHz ≤
tCYCP<180 MHz
Standard-mode
Min
Max
0
100
4.0
-
4.7
-
4.0
-
4.7
-
0
3.45*²
250
-
4.0
-
4.7
-
2tCYCP*⁴
-
4tCYCP*⁴
-
6tCYCP^*4
-
8tCYCP*⁴
-
10tCYCP*⁴
-
12tCYCP*⁴
-
14tCYCP*⁴
-
16tCYCP*⁴
-
Fast-mode
Min
Max
0
400
0.6
-
1.3
-
0.6
-
0.6
-
0
0.9*³
100
-
0.6
-
1.3
-
2tCYCP*⁴
-
4tCYCP*⁴
-
6tCYCP*⁴
-
8tCYCP*⁴
-
10tCYCP*⁴
-
12tCYCP*⁴
-
14tCYCP*⁴
-
16tCYCP*⁴
-
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
*5
1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
2: The maximum tHDDAT must not extend beyond the low period (tLOW) of the device’s SCL signal.
3: Fast-mode I²C bus device can be used on a Standard-mode I²C bus system as long as the device satisfies the
requirement of tSUDAT ≥ 250 ns.
4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I²C is connected, see
1.S6E2H Series Block Diagram in this data sheet.
When using Standard-mode, the peripheral bus clock must be set more than 2 MHz.
When using Fast-mode, the peripheral bus clock must be set more than 8 MHz.
5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB
bus clock frequency.
Document Number: 001-98943 Rev *C
Page 138 of 163