CYRF69213_08 Datasheet, PDF (54/76 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
USB Transceiver
USB Transceiver Configuration
Table 79. USB Transceiver Configure Register (USBXCR) [0x74] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
USB Pull-up
Enable
Reserved
USB Force
State
Read/Write
R/W
–
–
–
–
–
–
R/W
Default
0
0
0
0
0
0
0
0
Bit 7
USB Pull-up Enable
0 = Disable the pull-up resistor on D–
1 = Enable the pull-up resistor on D–. This pull-up is to V_CC IF VREG is not enabled or to the internally generated
3.3V when VREG is enabled. This bit should be cleared in sleep mode.
Bits 6:1 Reserved
Bit 0
USB Force State
This bit allows the state of the USB IO pins DP and D+ to be forced to a state while USB is enabled
0 = Disable USB Force State
1 = Enable USB Force State. Allows the D– and D+ pins to be controlled by P1.1 and P1.0 respectively when the
USBIO is in USB mode. Refer to Table 48 for more information
Note The USB transceiver has a dedicated 3.3V regulator for USB signalling purposes and to provide for the 1.5K D– pull up.
Unlike the other 3.3V regulator, this regulator cannot be controlled/accessed by firmware. When the device is suspended, this
regulator is disabled along with the bandgap (which provides the reference voltage to the regulator) and the D– line is pulled up
to 5V through an alternate 6.5K resistor. During wakeup following a suspend, the band gap and the regulator are switched on
in any order. Under an extremely rare case when the device wakes up following a bus reset condition and the voltage regulator
and the band gap turn on in that particular order, there is possibility of a glitch/low pulse occurring on the D– line. The host can
misinterpret this as a deattach condition. This condition, although rare, can be avoided by keeping the bandgap circuitry enabled
during sleep. This is achieved by setting the ‘No Buzz’ bit, bit[5] in the OSC_CR0 register. This is an issue only if the device is
put to sleep during a bus reset condition
VREG Control
Table 80. VREG Control Register (VREGCR) [0x73] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Keep Alive VREG En-
able
Read/Write
–
–
–
–
–
–
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bits 7:2 Reserved
Bit 1
Keep Alive
Keep Alive when set allows the voltage regulator to source up to 20 µA of current when voltage regulator is dis-
abled, P12CR[0],P12CR[7] should be cleared.
0 = Disabled
1 = Enabled
Bit 0
VREG Enable
This bit turns on the 3.3V voltage regulator. The voltage regulator only functions within specifications when V_CC is
above 4.35V. This block should not be enabled when V_CC is below 4.35V—although no damage or irregularities
will occur if it is enabled below 4.35V
0 = Disable the 3.3V voltage regulator output on the VREG/P1.2 pin
1 = Enable the 3.3V voltage regulator output on the VREG/P1.2 pin. GPIO functionality of P1.2 is disabled
Note Use of the alternate drive on pins P1.3–P1.6 requires that the VREG Enable bit be set to enable the regulator and provide
the alternate voltage
Document #: 001-07552 Rev. *C
Page 54 of 76
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