CYRF69213_08 Datasheet, PDF (51/76 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
Table 72. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved Prog Interval 1-ms Timer USB Active USB Reset USB EP2
Timer
USB EP1
USB EP0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt
Bit 7
Reserved
Table 73. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved Reserved Reserved GPIO Port 2 Reserved
INT2
16-bit
Counter
Wrap
Reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt
Bits 7,6,5,3,0Reserved
Interrupt Mask Registers
The Interrupt Mask Registers (INT_MSKx) are used to enable
the individual interrupt sources’ ability to create pending inter-
rupts.
There are four Interrupt Mask Registers (INT_MSK0,
INT_MSK1, INT_MSK2, and INT_MSK3), which may be referred
to in general as INT_MSKx. If cleared, each bit in an INT_MSKx
register prevents a posted interrupt from becoming a pending
interrupt (input to the priority encoder). However, an interrupt can
still post even if its mask bit is zero. All INT_MSKx bits are
independent of all other INT_MSKx bits.
If an INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that will become a
pending interrupt.
The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7]
determines the way an individual bit value written to an
INT_CLRx register is interpreted. When is cleared, writing 1's to
an INT_CLRx register has no effect. However, writing 0's to an
INT_CLRx register, when ENSWINT is cleared, will cause the
corresponding interrupt to clear. If the ENSWINT bit is set, any
0’s written to the INT_CLRx registers are ignored. However, 1’s
written to an INT_CLRx register, while ENSWINT is set, will
cause an interrupt to post for the corresponding interrupt.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level interac-
tions that are sometimes necessary to create a hardware-only
interrupt.
Table 74. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
ENSWINT
Reserved
Read/Write
R/W
–
–
–
–
–
–
–
Default
0
0
0
0
0
0
0
0
Bit 7
Bits 6:0
Enable Software Interrupt (ENSWINT)
0 = Disable. Writing 0’s to an INT_CLRx register, when ENSWINT is cleared, will cause the corresponding interrupt to clear
1 = Enable. Writing 1’s to an INT_CLRx register, when ENSWINT is set, will cause the corresponding interrupt to post
Reserved
Document #: 001-07552 Rev. *C
Page 51 of 76
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