CYRF69213_08 Datasheet, PDF (28/76 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
Table 39. USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Fine Tune USB Osclock
Only
Disable
Read/Write
–
–
–
–
–
–
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register is used to trim the Internal 24-MHz Oscillator using received low-speed USB packets as a timing reference. The
USB Osclock circuit is active when the Internal 24-MHz Oscillator provides the USB clock
Bits 7:2 Reserved
Bit 1
Fine Tune Only
0 = Enable
1 = Disable the oscillator lock from performing the course-tune portion of its retuning. The oscillator lock must be
allowed to perform a course tuning in order to tune the oscillator for correct USB SIE operation. After the oscillator
is properly tuned this bit can be set to reduce variance in the internal oscillator frequency that would be caused by
course tuning
Bit 0
USB Osclock Disable
0 = Enable. With the presence of USB traffic, the Internal 24-MHz Oscillator precisely tunes to 24 MHz ± 1.5%
1 = Disable. The Internal 24-MHz Oscillator is not trimmed based on USB packets. This setting is useful when the
internal oscillator is not sourcing the USBSIE clock
Table 40. Timer Clock Config (TMRCLKCR) [0x31] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
TCAPCL Divider
TCAPCLK Select
ITMRCLK Divider
ITMRCLK Select
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
-
-
-
-
1
1
0
0
Bits 7:6 TCAPCLK Divider
TCAPCLK Divider controls the TCAPCLK divisor
00 = Divide by 2
01 = Divide by 4
10 = Divide by 6
11 = Divide by 8
Bits 5:4 TCAPCLK Select
The TCAPCLK Select field controls the source of the TCAPCLK
0 0 = Internal 24-MHz Oscillator
0 1 = External crystal oscillator—external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is
enabled, CLKIN input if the external crystal oscillator is disabled (the XOSC Enable bit of the CLKIOCR Register is
cleared—Table 41)
1 0 = Internal 32-KHz Low-power Oscillator. However this configuration is not used in sleep mode.
1 1 = TCAPCLK Disabled
Note The 1024-μs interval timer is based on the assumption that TCAPCLK is running at 4 MHz. Changes in TCAPCLK frequency will cause
a corresponding change in the 1024-μs interval timer frequency
Bits 3:2 ITMRCLK Divider
ITMRCLK Divider controls the ITMRCLK divisor.
0 0 = Divider value of 1
0 1 = Divider value of 2
1 0 = Divider value of 3
1 1 = Divider value of 4
Bits 1:0 ITMRCLK Select
0 0 = Internal 24-MHz Oscillator
0 1 = External crystal oscillator – external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is
enabled, CLKIN input if the external crystal oscillator is disabled
1 0 = Internal 32-KHz Low-power Oscillator. However this configuration is not used in sleep mode.
1 1 = TCAPCLK
Document #: 001-07552 Rev. *C
Page 28 of 76
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