CYRF69213_08 Datasheet, PDF (30/76 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

Figure 10. Timer Capture Block Diagram
Captimer Clock
System Clock
Configuration Status
and Control
16-bit counter
Prescale Mux
CYRF69213
1ms
timer
Overflow
Interrupt
Capture Registers
Capture0 Int
Capture1 Int
Interrupt Controller
Table 41. Clock IO Config (CLKIOCR) [0x32] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
CLKOUT Select
Read/Write
–
–
–
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bits 7:2 Reserved
Bits 1:0
CLKOUT Select
0 0 = Internal 24-MHz Oscillator
0 1 = External crystal oscillator – external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is
enabled, CLKIN input if the external oscillator is disabled
1 0 = Internal 32-KHz Low-power Oscillator.However this configuration is not used in sleep mode.
1 1 = CPUCLK
CPU Clock During Sleep Mode
When the CPU enters sleep mode the CPUCLK Select (Bit [0],
Table 37) is forced to the internal oscillator, and the oscillator is
stopped. When the CPU comes out of sleep mode it is running
on the internal oscillator. The internal oscillator recovery time is
three clock cycles of the Internal 32-KHz Low-power Oscillator.
If the system requires the CPU to run off the external clock after
awakening from sleep mode, firmware will need to switch the
clock source for the CPU.
Reset
The microcontroller supports two types of resets: Power-on
Reset (POR) and Watchdog Reset (WDR). When reset is
initiated, all registers are restored to their default states and all
interrupts are disabled.
The occurrence of a reset is recorded in the System Status and
Control Register (CPU_SCR). Bits within this register record the
occurrence of POR and WDR Reset respectively. The firmware
can interrogate these bits to determine the cause of a reset.
The microcontroller resumes execution from Flash address
0x0000 after a reset. The internal clocking mode is active after a
reset, until changed by user firmware.
Note The CPU clock defaults to 3 MHz (Internal 24-MHz Oscil-
lator divide-by-8 mode) at POR to guarantee operation at the low
V_CC that might be present during the supply ramp.
Document #: 001-07552 Rev. *C
Page 30 of 76
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