CYRF69213_08 Datasheet, PDF (10/76 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
SPI Connects to External Devices
The three SPI wires, MOSI, SCK, and SS are also drawn out of
the package as external pins to allow the user to interface their
own external devices (such as optical sensors and others)
through SPI. The radio function also has its own SPI wires MISO
and IRQ, which can be used to send data back to the MCU
function or send an interrupt request to the MCU function. They
can also be configured as GPIO pins.
Figure 6. SPI Transaction Format
Byte 1
Bit#
7
6
[5:0]
Bit Name DIR
INC
Address
[7:0]
Data
Byte 1+N
CPU Architecture
This family of microcontrollers is based on a high-performance,
8-bit, Harvard-architecture microprocessor. Five registers
control the primary operation of the CPU core. These registers
are affected by various instructions, but are not directly acces-
sible through the register space by the user.
Table 4. CPU Registers and Register Names
Register
Flags
Program Counter
Accumulator
Stack Pointer
Register Name
CPU_F
CPU_PC
CPU_A
CPU_SP
Index
CPU_X
The 16-bit Program Counter Register (CPU_PC) allows for direct
addressing of the full eight Kbytes of program memory space.
The Accumulator Register (CPU_A) is the general-purpose
register that holds the results of instructions that specify any of
the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addressing modes. Typically, this is used to
address a block of data within the data memory space.
The Stack Pointer Register (CPU_SP) holds the address of the
current top-of-stack in the data memory space. It is affected by
the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It can also be affected by the
SWAP and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] is used to globally enable or disable inter-
rupts. The user cannot manipulate the Supervisory State status
bit [3]. The flags are affected by arithmetic, logic, and shift opera-
tions. The manner in which each flag is changed is dependent
upon the instruction being executed (for example, AND, OR,
XOR). See Table 21.
Document #: 001-07552 Rev. *C
Page 10 of 76
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