CYRF69213_08 Datasheet, PDF (37/76 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
Table 48. P1 Data Register (P1DATA) [0x01] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
P1.7
P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG P1.1/D–
P1.0/D+
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 1 pins
Bit 7
P1.7 Data
Bits 6:3
P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)
In addition to their use as the P1.6–P1.3 GPIOs, these pins can also be used for the alternative function as the SPI
interface pins. To configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (Table 56)
The use of the pins as the P1.6–P1.3 GPIOs and the alternative functions exist in all the CYRF69213 parts
Bit 2
P1.2/VREG
This pin is used as the regulator output. The 3.3V VREG output must be enabled by setting Bit 0 of VREGCR register
(Table 80). A 1-mF min, 2-mF max capacitor is required on VREG output.
Bits 1:0
P1.1–P1.0/D– and D+
When USB mode is disabled (Bit 7 in Table 81 is clear), the P1.1 and P1.0 bits are used to control the state of the P1.0
and P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– and D+ pins, respectively.
If the USB Force State bit (Bit 0 in Table 79) is set, the state of the D– and D+ pins can be controlled by writing to the
D– and D+ bits
Table 49. P2 Data Register (P2DATA) [0x02] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
P2.1–P2.0
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 2 pins
Bits 7:2 Reserved Data [7:2]
Bits 1:0 P2 Data [1:0]
GPIO Port Configuration
All the GPIO configuration registers have common configuration
controls. The following are the bit definitions of the GPIO config-
uration registers.
Int Enable
When set, the Int Enable bit allows the GPIO to generate inter-
rupts. Interrupt generate can occur regardless of whether the pin
is configured for input or output. All interrupts are edge sensitive,
however for any interrupt that is shared by multiple sources (that
is, Ports 2, 3, and 4) all inputs must be deasserted before a new
interrupt can occur.
When clear, the corresponding interrupt is disabled on the pin.
It is possible to configure GPIOs as outputs, enable the interrupt
on the pin and then to generate the interrupt by driving the appro-
priate pin state. This is useful in test and may have value in appli-
cations as well.
Int Act Low
When set, the corresponding interrupt is active on the falling
edge.
When clear, the corresponding interrupt is active on the rising
edge.
TTL Thresh
When set, the input has TTL threshold. When clear, the input has
standard CMOS threshold.
High Sink
When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA.
On the CYRF69213, only the P1.7–P1.3 have 50-mA sink drive
capability. Other pins have 8-mA sink drive capability.
Open Drain
When set, the output on the pin is determined by the Port Data
Register. If the corresponding bit in the Port Data Register is set,
the pin is in high-impedance state. If the corresponding bit in the
Port Data Register is clear, the pin is driven low.
When clear, the output is driven LOW or HIGH.
Document #: 001-07552 Rev. *C
Page 37 of 76
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