BCM43236BKMLG Datasheet, PDF (38/43 Pages) Cypress Semiconductor – 2.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio Chip

BCM43236/BCM43236B Preliminary Data Sheet
Serial Flash Timing Diagram
Serial Flash Timing Diagram
Figure 10: Serial Flash Timing Diagram (STMicroelectronics-Compatible)
t_CS
SFLASH_CS_L
SFLASH_C
t_CSS
t_WL
t_WH
t_SU
t_H
t_R
t_F
t_CSH
SFLASH_Q
VALID IN
SFLASH_D
High Impedance
t_V
t_HO
VALID ON
High Impedance
Table 19: Serial Flash Timing
Parameter Descriptions
f_SCK
t_WH
t_WL
t_R, t_Fa
t_CSS
t_CS
t_CSH
t_SU
t_H
t_HO
t_V
Serial flash clock frequency
Serial flash clock high time
Serial flash clock low time
Clock rise and fall times^b
Chip select active setup time
Chip select deselect time
Chip select hold time
Data input setup time
Data input hold time
Data output hold time
Clock low to output valid
a. t_R and t_F are expressed as a slew-rate.
b. Peak-to-peak
Minimum Typical
–
12.5
9
–
9
–
TBD
–
5
–
100
–
5
–
2
–
5
–
0
–
–
–
Maximum
66
–
–
–
Units
MHz
ns
ns
V/ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
8
ns
BROADCOM ®
September 16, 2013 • 43236_43236B-DS103-R
Page 37