BCM43236BKMLG Datasheet, PDF (12/43 Pages) Cypress Semiconductor – 2.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio Chip

BCM43236/BCM43236B Preliminary Data Sheet
Functional Description
Section 2: Functional Description
Global Functions
Power Management
The BCM43236/BCM43236B chips have been designed with the stringent power consumption requirements of
battery-powered hosts in mind. All areas of the chip design were scrutinized to help reduce power
consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages.
The BCM43236/BCM43236B chips include an advanced Power Management Unit (PMU). The PMU provides
significant power savings by putting the BCM43236/BCM43236B into various power management states
appropriate to the current environment and activities that are being performed. The power management unit
enables and disables internal regulators, switches, and other blocks based on a computation of the required
resources and a table that describes the relationship between resources and the time needed to enable and
disable them. Power-up sequences are fully programmable. Configurable, free-running counters in the PMU
are used to turn on/off individual regulators and power switches. Clock speeds are dynamically changed (or
gated altogether) for the current mode. Slower clock speeds are used wherever possible.
Voltage Regulators
Three Low-Dropout (LDO) regulators and a PMU are integrated into the BCM43236/BCM43236B. All regulators
are programmable via the PMU.
Reset
Resets are generated internally by the BCM43236/BCM43236B. An optional external power-on reset circuit can
be connected to the active-low Ext_por input pin. A 50 ms low pulse is recommended to guarantee that a
sufficiently long reset is applied to all internal circuits, including integrated PHYs. The initialization process loads
all pin-configurable modes, resets all internal processes, and puts the device in the idle state. During
initialization, the clock source input signal must be active, and the 3.3V power supply to the device must be
stable. The external power-on reset overrides the BCM43236/BCM43236B internal reset.
GPIO Interface
There are eight General-Purpose I/O (GPIO) pins provided on the BCM43236/BCM43236B. They are
multiplexed with the control signals. These pins can be used to attach to various external devices. Upon power-
up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output
pins via the GPIO control register. A programmable internal pull-up/pull-down resistor is included on each
GPIO. If a GPIO output enable is not asserted, and the corresponding GPIO signal is not being driven externally,
the GPIO state is determined by its programmable resistor.
BROADCOM ®
September 16, 2013 • 43236_43236B-DS103-R
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