BCM43236BKMLG Datasheet, PDF (37/43 Pages) Cypress Semiconductor – 2.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio Chip

BCM43236/BCM43236B Preliminary Data Sheet
Timing Characteristics
Section 7: Timing Characteristics
Reset and Clock Timing Diagram
Resets are generated internally by the BCM43236/BCM43236B chips. An optional external Power-On Reset
(POR) circuit can be connected to the active-low Ext_por input pin. The BCM43236/BCM43236B chips are reset
automatically as long as the power supplies are turned on in the following sequence. 3.3V first, 2.5V second,
and 1.2V last.
Figure 9: Timing for the Optional External Power-On Reset
Vcc
WPLL_CLK25
(20 MHz)
Ext_por
Configuration
Strap Signals
t210
t204
t201
t203
t202
t206
t207 t208
t205
t209
Valid
Table 18: Ext_por and Clock Timing
Parameter Description
Minimum Typical
t201
OSCIN frequency
19.9995 20.0000
t202
OSCIN high time
–
20
t203
OSCIN low time
–
20
t204
EXT_POR_L low pulse duration
50
–
t207
Configuration valid setup to EXT_POR_L rising 50
–
t208
Configuration valid hold from EXT_POR_L rising 1.7
–
t209
EXT_POR_L deassertion to normal switch
–
3
operation
t210
Reset low hold time after power supplies
50
–
stabilize
Maximum Units
20.0005 MHz
–
ns
–
ns
–
ms
–
μs
2.8
ms
–
ms
–
ms
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September 16, 2013 • 43236_43236B-DS103-R
Page 36