BCM43236BKMLG Datasheet, PDF (27/43 Pages) Cypress Semiconductor – 2.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio Chip

BCM43236/BCM43236B Preliminary Data Sheet
Strapping Options
Table 3: Signal Descriptions (Cont.)
Signal
BCM43236/
BCM43236B Type
analog_wlan_iqtest_vdd_1p2 17
PWR
ldo_3p3_in
57
PWR
vddpll/rf_avdd_1p2
59
O
vreg3p3_vdd3p3
45
PWR
i_xtal_vdd2p5/o_xtal_vdd2p5 50
O
vref
56
–
paref
55
–
paref_ctl1
54
–
paref_ctl2
53
–
gnd_slug
H
GND
gnd
24
GND
Description
1.2V power supply for IQ test.
3.3V input to RF LDO
XTAL power reference; decouple to ground.
Analog 3.3V supply
Connect with bypass cap.
VREF; decouple to ground.
PA reference; decouple to ground.
PA reference control 1
PA reference control 2
Ground
Ground
Strapping Options
The pins listed in Table 4 are sampled at Power-on Reset (POR) to determine the various operating modes.
Sampling occurs within a few milliseconds following internal POR or deassertion of external POR. After POR,
each pin assumes the function specified in the signal descriptions table. Each pin has an internal pull-up (PU)
or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU
resistor to VDDIO or a PD resistor to GND; use 10 kΩ or less (refer to the reference board schematics for further
details).
Signal Name
mimophy_core0_ant0_tx
mimophy_core1_ant0_tx
mimophy_core0_ant0_rx
mimophy_core0_ant1_tx
mimophy_core0_ant1_rx
gpio[7:6]
Table 4: Strapping Options
Mode
OTP select
SFLASH not
present
ST SFLASH
USB PHY
120 MHz
Boot from ROM
Default
PU
PD
PD
PU
PU
No pull
Description
0: No OTP
1: OTP present
0: SFLASH not present
1: SFLASH present
0: SFLASH type is STMicroelectronics
1: SFLASH type is Atmel®
0: HSIC mode
1: USB PHY mode
0: Backplane at 96 (98.4) MHz
1: Backplane at 120 (123) MHz
00: Remap to RAM; ARM processor to be held at
reset.
01: Boot from ROM unless the ARM needs to be
held at reset.
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September 16, 2013 • 43236_43236B-DS103-R
Page 26