BCM43236BKMLG Datasheet, PDF (15/43 Pages) Cypress Semiconductor – 2.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio Chip

BCM43236/BCM43236B Preliminary Data Sheet
Global Functions
The endpoint management unit contains the PIE control logic and the endpoint logic. The PIE interfaces
between the packet buffers and the USB transceiver. It handles packet identification (PID), USB packets, and
transactions.
The endpoint logic contains nine uniquely-addressable endpoints. These endpoints are the source or sink of
communication flow between the host and the device. Endpoint zero is used as a default control port for both
the input and output directions. The USB system software uses this default control method to initialize and
configure the device information, and allows USB status and control access. Endpoint zero is always accessible
after a device is attached, powered, and reset.
Endpoints are supported by 512-byte FIFO buffers, one for each IN endpoint and one shared by all OUT
endpoints. Both TX and RX data transfers support a DMA burst of 4, which guarantees low latency and
maximum throughput performance. The RX FIFO can never overflow by design. The maximum USB packet size
cannot be more than 512 bytes.
The BCM43236/BCM43236B can be configured as a USB 2.0 device or as a PHY-less HSIC by selecting the
appropriate strapping option. See Table 4 on page 26 for information on how to select the strapping options.
Crystal Oscillator
Table 1 lists the requirements for the crystal oscillator.
Table 1: Crystal Oscillator Requirements
Parameter
Frequency
Mode
Load capacitance
ESR
Frequency stability
Aging
Drive level
Q-factor
Shunt capacitance
Value
20 MHz
AT cut, fundamental
16 pF
50Ω maximum
±10 ppm at 25°C
±10 ppm at 0°C to +85°C
±3 ppm/year max first year, ±1 ppm thereafter
300 µW maximum
40,000 minimum
< 5 pF
Figure 5 shows the recommended oscillator configuration.
BROADCOM ®
September 16, 2013 • 43236_43236B-DS103-R
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