BCM43236BKMLG Datasheet, PDF (30/43 Pages) Cypress Semiconductor – 2.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio Chip

BCM43236/BCM43236B Preliminary Data Sheet
HSIC Characteristics
HSIC Characteristics
Table 9: HSIC Characteristics
Parameter
Symbol Minimum Typical
Maximum Unit Comments
HSIC signaling voltage
V_DD
I/O voltage input low
V_IL
I/O Voltage input high
V_IH
I/O voltage output low V_OL
I/O voltage output high V_OH
I/O pad drive strength
O_D
I/O weak keepers
I_L
I/O input impedance
Z_I
Total capacitive load^a
C_L
1.1
1.2
–0.3
–
0.65 × V_DD –
–
–
0.75 × V_DD –
40
–
20
–
100
–
3
–
1.3
V
0.35 × V_DD V
V_DD + 0.3 V
0.25 × V_DD V
–
V
60
Ω
70
mA
–
kΩ
14
pF
–
–
–
–
–
Controlled output
impedance driver
–
–
–
Characteristic trace
T_I
45
50
55
Ω
–
impedance
Circuit board trace length T_L
–
–
10
cm –
Circuit board trace
T_S
–
–
15
ps
–
propagation skew^b
STROBE frequency^c
F_STROBE 239.988
240
Slew rate (rise and fall) T_slew
STROBE and DATA^C
0.60 × V_DD 1.0
Receiver data setup time T_s
300
–
(with respect to STROBE)^c
240.012
1.2
–
MHz ± 500 ppm
V/ns Averaged from
30% ~ 70% points
ps
Measured at the
50% point
Receiver data hold time T_b
300
–
–
ps
Measured at the
(with respect to STROBE)^c
50% point
a. Total Capacitive Load (C_L), includes device Input/Output capacitance, and capacitance of a 50Ω PCB trace with
a length of 10 cm.
b. Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be
matched between STROBE and DATA to ensure that the signal timing is within specification limits at the
receiver.
c. Jitter and duty cycle are not separately specified parameters: they are incorporated into the values in the table
above.
BROADCOM ®
September 16, 2013 • 43236_43236B-DS103-R
Page 29