BCM43236BKMLG Datasheet, PDF (14/43 Pages) Cypress Semiconductor – 2.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio Chip

BCM43236/BCM43236B Preliminary Data Sheet
Global Functions
USB/HSIC Interface
The BCM43236/BCM43236B USB/HSIC interface can be set to operate as a USB 2.0 port or a High-Speed Inter-
Chip (HSIC) port. Features of the interface are:
• USB 2.0 protocol engine:
– Parallel Interface Engine (PIE) between packet buffers and USB transceiver
– Supports up to nine endpoints, including Configurable Control Endpoint 0
• Separate endpoint packet buffers with a 512-byte FIFO buffer each
• Host-to-device communication for bulk, control, and interrupt transfers
• Configuration/status registers
• The HSIC port can communicate with an external HSIC host, such as the BCM5357 and BCM5358.
The various blocks in the USB 2.0 device/HSIC core are shown in Figure 4.
Figure 4: USB 2.0 Device/HSIC Core Block Diagram
32-bit On-Chip Communication System
USB 2.0 Device
or HSIC
DMA Engines
RX
FIFO
FFTFITFIFFTIXFTIXIFOTXFOFXOXOOs
Endpoint Management Unit
USB 2.0
Protocol Engine
HSIC PHY
USB 2.0 PHY
Data
Strobe
D+
D-
The USB 2.0 PHY handles the USB protocol and the serial signaling interface between the host and device. It is
primarily responsible for data transmission and recovery. On the transmit side, data is encoded, along with a
clock, using the NRZI scheme with bit stuffing to ensure that the receiver detects a transition in the data
stream. A SYNC field that precedes each packet enables the receiver to synchronize the data and clock recovery
circuits. On the receive side, the serial data is deserialized, unstuffed, and checked for errors. The recovered
data and clock are then shifted to the clock domain that is compatible with the internal bus logic.
BROADCOM ®
September 16, 2013 • 43236_43236B-DS103-R
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