STC3800_15 Datasheet, PDF (6/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

Absolute Maximum Ratings
Table 2
Symbol Parameter
Minimum
Nominal Maximum Units Notes
Vdd2.5
Logic power supply voltage, 2.5V
-0.3
-
3.0
Volts
1
Vdd3.3
Logic power supply voltage 3.3V
-0.3
-
4.0
Volts
1
AVdd2.5 Analog power supply voltage, 2.5V
-0.3
-
4.0
Volts
1
VIN
Logic input voltage, rel. to GND
-0.3
-
Vdd3.3 + 0.5 Volts
1
TSTG
Storage Temperature
-55
-
110
°C
1
Note 1: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.
Recommended Operating Conditions & Electrical Characteristics
Table 3
Symbol Parameter
Minimum
Nominal Maximum
Vdd2.5
2.5V digital power supply voltage
2.3
2.5
2.7
Vdd3.3
3.3V digital power supply voltage
3.0
3.3
3.6
AVdd2.5 2.5V analog power supply voltage
2.3
2.5
2.7
VIH (3.3V)
VIL (3.3V)
High level input voltage
Low level input voltage
2.0
-
Vdd3.3 + 0.3
0.3
-
0.8
VOH (3.3V) High level output voltage (IOH = -7mA) 0.9*Vdd3.3
-
-
VOL (3.3V) Low level output voltage (IOL =10mA)
-
-
0.4
VIL (PECL) Low level input voltage (PECL inputs)
VOH (PECL) High level input voltage (PECL inputs)
VID (PECL) PECL differential input voltage
0.86
1.49
0.3
-
2.125
-
2.72
-
Vdd3.3
CIN
Input capacitance
-
THL
Clock fall time (TCXO, OCXO, VCXO)
-
-
10
-
5
TLH
Clock rise time (TCXO, OCXO, VCXO)
-
-
5
TRIP
Input reference signal positive pulse width 10
TRIN
Input reference signal negative pulse width 10
-
-
-
-
TA
Operating Ambient Temperature Range
0
Icc (Vdd2.5) 2.5V digital supply current
-
-
70
-
500
Icc (Vdd3.3) 3.3V digital supply current
-
-
200
Icc (Avdd2.5) 2.5V analog supply current
-
-
50
Pd
Device power dissipation
Note 2: LVTTL compatible
-
-
2.0
Units
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
pF
nS
nS
nS
nS
°C
mA
mA
mA
W
Register Map
Table 4
Address Reg Name
0x00
Chip_ID_Low
0x01
Chip_ID_High
0x02
Chip_Revision
0x03
Bandwidth_PBO
0x04
Ctl_Mode
0x05
Op_Mode
Description
Low byte of chip ID
High byte of chip ID
Chip revision number
Bandwidth & Phase Build-Out option
Manual or automatic selection of Op_Mode,
BITS clock output frequency indication,
and frame/multi-frame sync pulse width mode control
Master Free Run, Locked, or Hold Over mode, or Slave mode
Notes
2
2
2
2
Type
R
R
R
R/W
R/W
R/W
Preliminary Data Sheet #: TM061 Page 6 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice