STC3800_15 Datasheet, PDF (43/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

Application Notes continued
Set the device bandwidth and enable/disable phase build-out by writing the appropriate values to the Bandwidth_PBO
register, 0x03. (See Register Descriptions and Operation). The recommended value is .098 Hz for Stratum 3 and
0.77 MHz for Stratum 3E. Set bit 4 to “1” to enable Phase build-out, “0” to disable. Typically, per the Telcordia
requirements, phase build-out for active reference hits is enabled for Stratum 3E and disabled for Stratum 3. Therefore,
the recommended values are:
Stratum
3
3E
Reg. 0x03
0000 0111
0001 0000
For Stratum 3E applications, note that the ability to achieve and maintain lock depends on the stability of the oscillator.
If the oscillator is drifting excessively, the device may not be able to lock or stay locked. This is particularly an issue
when the oscillator is warming up and the bandwidth is set very low. In some cases, an oscillator may be needed to
warm up for extended periods of time (Hours to a few days) to be sufficiently stable to lock with the lowest bandwidths,
e.g. .84 mHz.
The application will need to review the specifications of the oscillator of intended use, and may need to perform some
tests to determine adequate warm-up times for particular bandwidths. The application may also choose to progressively
narrow the bandwidth in conjunction with the warm-up period.
Select manual active reference by writing bit 1 of the Ctrl_Mode register (0x04) to 1.
Select 50% duty cycle or variable pulse width for the Sync_8K and Sync_2K output by writing the appropriate values
to bits 4 and 5 of the Ctl_Mode register (0x04), as shown below:
Pulse Width Control
Sync_2K and Sync_8K 50% duty cycle
Sync_2K 50% duty cycle, Sync_8K variable pulse width
Sync_2K variable pulse width, Sync_8K 50% duty cycle
Sync_2K and Sync_8K variable pulse width
Reg. 0x03 BITS 5-4
00
01
10
11
In variable pulse width mode, the desired pulse width is written to register FR_Pulse_Width (0x10). The pulse width is
the register value (valid range is 1 - 15) multiple of the Sync_Clk clock period. The same pulse width is applied to both
Sync_8K and Sync_2K. For example, if Sync_Clk is at 19.44 MHz and the desired pulse width is 206nS, write
FR_Pulse_Width to 0000 0100 (4 x 51.5nS).
The auto-detected reference input freqencies may be read from bits -4 of the Ref(1-8)_Frq_Priority registers.
If desired, write the Freerun_Priority register (0x24) to enable Free Run to be treated like a reference (See Register
Description and Operation section). If it is enabled, set the desired priority and revertivity.
Preliminary Data Sheet #: TM061 Page 43 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice