STC3800_15 Datasheet, PDF (30/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

Application Notes
This section describes typical application use of the STC3800 device. The General section applies to all application
variations, while the remaining sections detail use depending on the level of control and automatic operation the
application desires.
General
Power and Ground – Well-planned noise-minimizing power and ground are essential to achieving the best
performance of the device. The device requires 2.5V and 3.3V digital power and 2.5V analog power input. All digital I/O
is at 3.3V, LVTTL compatible. The 2.5V may originate from a common source but should be individually filtered and
isolated, as shown in Figure 8. Alternatively, a separate 2.5V regulator may be used for the analog 2.5 volts. R/C filter
components should be chosen for minimum inductance and kept as close to the chip as possible.
Note the ferrite bead power filter and bypass capacitors associated with the oscillator power. Mount the bypass
capacitors as close to the oscillators as possible. Oscillator and EEPROM ground is the digital ground.
It is desirable to provide individual bypass capacitors, located close to the chip, for each of the digital power input
leads, subject to board space and layout constraints. On power-up, it is desirable to have the 3.3V either lead or be
coincident with, but not lag the application of 2.5V.
Digital ground should be provided by as continuous a ground plane as possible. While the analog and digital grounds
are tied together inside the chip, it is recommended that they be tied together externally at a single point close to the
chip as well.
Peripherals – Peripheral connections are also shown in Figure 9:
The OCXO/TCXO output is connected to the M_Clk pin. VCXOs up to 77.76 MHz connect to the VC_TTL pin, and the
device is configured for TTL input by tying the VC_Sel pin high. If the VCXO is at 155.52 MHz, its output will typically be
PECL compatible and should be connected to the VC_PPECL and VC_NPECL pins. Tie the VC_Sel pin low for PECL
input. For 155.52 MHz operation, a PECL buffer will also need to be provided for the 155.52 MHz clock output.
Digital to analog converter clock, data, and chip select connect to pins DACclk, DACdin, and DACld, respectively. The
DAC output is connected to the VCXO input through a simple R/C filter as shown in Figure 9 below. The capacitors
preferably are tantalum.
If the optional EEPROM is included, serial clock, serial data, and WP connect to pins E²scl, E²sda, and E²wp,
respectively. The Dmode pin selects the source for configuration data, 0 = from the bus interface, 1 = from the
EEPROM.
Preliminary Data Sheet #: TM061 Page 30 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice