STC3800_15 Datasheet, PDF (19/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

Register Descriptions and Operation continued
Op_Mode, 0x05 (R/W)
Bit 7 ~ Bit 5
Reserved
Bit 4
Master or Slave Mode
1: Master
0: Slave
(read-only)
Bit 3 ~ Bit 0
Free Run, Locked, or Hold Over:
0000: Free Run mode
0001: Locked on Ref1
0010: Locked on Ref2
0011: Locked on Ref3
0100: Locked on Ref4
0101: Locked on Ref5
0110: Locked on Ref6
0111: Locked on Ref7
1000: Locked on Ref8
1001 - 1111: Hold Over
When HM_Ref = 1, enabling hardware control of reference selection and operational mode control, bits 3 - 0 of this register
are read-only and reflect the state of the device as set by the Sel3-0 pin inputs.
Bit 4 of this register is read-only and follows the state of the M/S pin.
When the device is in slave mode, it will lock to the Xref input, independent of the values written to bits 3 - 0 of the Op_mode
register. The operational mode and reference selection written to bits 3 - 0 while in slave mode will, however, take effect
when the device is made the master.
When bit 1 of the Ctl_Mode register is reset (automatic reference and mode selection) and the device is in master mode,
bits 3 - 0 of the Op_Mode register become read-only.
Max_Pullin_Range, 0x06 (R/W)
Maximum pull-in range in 0.1 ppm unit
Bit 7 ~ Bit 0
This register should be set according to the values specified by the standards (GR-1244) appropriate for the particular stratum of
operation. The power-up default value is 10 ppm. (=4.6 ppm aging + 4.6 ppm pull-in + margin)
Xref_Activity, 0x07 (R)
Bit 7 ~ Bit 4
Reserved
Indicates signal presence and auto-detected frequency for the Xref input.
Bit 3 ~ Bit 0
Xref signal/frequency
0000: No Signal
0001: 8 kHz
0100: 12.96 MHz
0101: 19.44 MHz
0110: 25.92 MHz
0111: 38.88 MHz
1000: 51.84 MHz
1001: 77.76 MHz
1010-111: Reserved
Ref_Activity, 0x08 (R)
Bit 7
Bit 6
ref8 activity ref7 activity
1: on
1: on
0: off
0: off
Bit 5
ref6 activity
1: on
0: off
Bit 4
ref5 activity
1: on
0: off
Each bit indicates the presence of a signal for that reference.
Bit 3
ref4 activity
1: on
0: off
Bit 2
ref3 activity
1: on
0: off
Bit 1
ref2 activity
1: on
0: off
Bit 0
ref1 activity
1: on
0: off
Preliminary Data Sheet #: TM061 Page 19 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice