STC3800_15 Datasheet, PDF (12/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

Detailed Description continued
Register Control – Bus/Register access is available in 8-bit parallel or SPI form, as selected by the Bmode pin. Bmode=1
selects parallel bus access, and Bmode=0 selects SPI. Parallel bus and SPI data I/O operations are shown as follows.
CS
t_CA
ALE
R/W
RDY
t_CR
AD
Parallel Bus Timing, Read Access
Figure 3
t_ALE
t_AR
t_RWs
t_RWh
t_As
t_Ah
Address
t_RDY
t_RC
t_RDs
t_RDh
Read Data
Parallel Bus Timing, Write Access
Figure 4
CS
ALE
R/W
t_CA
t_ALE
t_AR
t_RWs
t_RWh
RDY
t_CR
AD
t_As
t_Ah
Address
t_RDY
t_RC
t_WDs t_WDh
WriteData
t_CSMIN
t_CR
t_CSMIN
t_CR
Symbol
t_CA
t_ALE
t_AR
t_RWs
t_RWh
t_RDY
t_RC
t_CR
t_As
t_Ah
t_RDs
t_RDh
t_WDs
t_WDh
t_CSMIN
Parallel Bus Timing
Table 6
Parameter
Minimum
CS low to ALE low
0
ALE low time
70
ALE high to RDY low
-
R/W setup time
50
R/W hold time
50
RDY low time
100
RDY high to CS high
-
CS to RDY active/tristate time
-
Address setup time
50
Address hold time
50
Read data setup time
50
Read data hold time
50
Write data setup time
50
Write data hold time
50
Minimum delay between successive accesses 300
Nominal
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Maximum
-
-
250
-
-
-
0
10
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Data Sheet #: TM061 Page 12 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice