STC3800_15 Datasheet, PDF(44/48 Page) Connor-Winfield Corporation

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

STC3800_15 Datasheet, PDF (44/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

◁

Application Notes continued

Select the desired operational mode and reference by writing the appropriate value to register Op_Mode (0x05). (Note:

Reference switches are performed in a hitless manner. However, if the application externally changes the frequency of a

particular reference, the device requires 20mS to auto-detect the new frequency. Manual switches to a frequency

changed reference should not be made during this interval.)

Mode

Free Run

Lock on Ref1

Lock on Ref2

Lock on Ref3

Lock on Ref4

Lock on Ref5

Lock on Ref6

Lock on Ref7

Lock on Ref8

Hold Over

Reg. 0x03

0001 0000

0001 0001

0001 0010

0001 0011

0001 0100

0001 0101

0001 0110

0001 0111

0001 1000

0001 1001

When the device is in slave mode, it will lock to the Xref input, independent of the values written to bits 4 - 0 of the

Op_mode register. The operational mode and reference selection written to bits 4 - 0 while in slave mode will,

however, take effect when the device is made the master.

For simplex operation, the device should be in Master mode.

Select the desired Hold Over history policy, âContinueâ or âRebuildâ, by writing to the History_Policy register, (ox25).

The application may further save, restore, or flush the Hold Over history using the History_Cmd register (2x26), as

described in the Hold Over History Accumulation and Maintenance section.

The remainder of the registers provide access to device internals, such as synchronization state, reference activity and

quality, and operational customizations. Their use is at the discretion of the application. Some typical uses are

described below (see also the Register Descriptions and Operation section):

Max_Pullin_Range (0x06) - Set to the maximum allowed frequency offset for a reference.

Ref_Qualified (0x0a) - May be read to determine if a reference is active and within the pull-in range before selecting it

as an active reference.

MS_Phase_Offset (0x0e) - May be used to compensate for master/slave Sync_8K or Sync_Clk to Xref pathlength or

clock distribution paths, as desired. Requires analytic/experimental technique to determine appropriate values. See

also Master/Slave Operation sections.

Calibration (0x0f) - This register can be used to compensate for a known OCXO/TCXO frequency offset. Write to a

value representing the difference between the oscillatorâs measured frequency and the nominal frequency.

DPLL_Status (0x11) - This register provides active reference, lock, and Hold Over history status in support of mode

control decisions by the application.

Interrupts - Five interrupts are provided for application monitoring and control of synchronization. They are individually

maskeable by the Intr_Enable register (0x13), and readable in the Intr_Event (0x12) register. Pin INTR is pulled low

when a non-masked interrupt occurs.

Ctl_Mode (0x04) - The state of the BITS_Sel and HM_Ref pins may be read from bits 2 and 3.

Hold Over_Time - (0x27) - The time, from 0 to 255 hours, since the Hold Over state was entered, may be read.

While the same information is available via register access, the LOS, LOL, and Hold_Avail status indication outputs

are also functional and may be used at the discretion of the application.

Preliminary Data Sheet #: TM061 Page 44 of 48 Rev: P06 Date: 11/22/04

▷