STC5415 Datasheet, PDF (2/48 Pages) Connor-Winfield Corporation – Line Card Clock

STC5415
Line Card Clock
Data sheet
Table of Contents
STC5415 Pin Diagram (Top View) .................................................................................................................... 5
STC5415 Pin Description .................................................................................................................................. 6
Register Map ..................................................................................................................................................... 8
Master Clock Frequency .................................................................................................................................. 10
Input and Output Frequencies ......................................................................................................................... 11
Input Frequencies .................................................................................................................................... 11
Auto-Detect Acceptable Input Frequencies ...................................................................................... 11
Manually Acceptable Input Frequencies .......................................................................................... 11
Clock Output Frequencies ....................................................................................................................... 12
Clock Output Jitter ................................................................................................................................... 13
General Description ......................................................................................................................................... 14
Application ............................................................................................................................................... 14
Overview .................................................................................................................................................. 14
Chip Master Clock .................................................................................................................................... 14
Reference Inputs and External Sync Input .............................................................................................. 14
External Frame Sync Input ............................................................................................................... 14
Timing Generators and Operation Modes ................................................................................................ 14
Phase Synchronization ............................................................................................................................ 15
Clock Outputs .......................................................................................................................................... 15
Control Interfaces ..................................................................................................................................... 15
Field Upgradability ................................................................................................................................... 15
Advantage and Performance ................................................................................................................... 15
Detailed Description ......................................................................................................................................... 16
Chip Master Clock .................................................................................................................................... 16
Operation Mode ....................................................................................................................................... 16
PLL Event In ............................................................................................................................................ 16
Frame Phase Relationship ....................................................................................................................... 17
Frame Phase Arbitrary ..................................................................................................................... 17
Frame Phase Align ........................................................................................................................... 17
History of Fractional Frequency Offset .................................................................................................... 17
Short-Term History ........................................................................................................................... 17
Device Holdover History ................................................................................................................... 17
Phase-Locked Loop Status Details .......................................................................................................... 17
External SYNC Input and Reference Inputs Details ................................................................................ 18
External Frame Sync Inputs ............................................................................................................. 18
Acceptable Frequency and Frequency Offset Detection .................................................................. 18
Activity Monitoring ............................................................................................................................ 18
Input Qualification ............................................................................................................................ 19
Automatic Reference Election Mechanism ...................................................................................... 20
Automatic Reference Selection ........................................................................................................ 20
Manual Reference Selection Mode .................................................................................................. 20
Hard-wired Manual Reference Selection ......................................................................................... 20
Clock Outputs Details .............................................................................................................................. 21
Clock Synthesizers ........................................................................................................................... 21
Clock Generators ............................................................................................................................. 21
Clock Output Phase Alignment ........................................................................................................ 21
Synthesizer Skew Programming ...................................................................................................... 21
Clock Outputs ................................................................................................................................... 21
Event Interrupts ........................................................................................................................................ 21
Preliminary
Page 2 of 48 TM120
Rev:P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 20, 2011