STC5415 Datasheet, PDF (18/48 Pages) Connor-Winfield Corporation – Line Card Clock

STC5415
Line Card Clock
Data sheet
OOP bit
This bit indicates that the selected reference is out of
the pull-in range. This is meaningful only if in exter-
nal-timing mode. This bit will not be asserted in self-
timing mode. The frequency offset is relative to the
digitally calibrated freerun clock.
SAP bit
This bit when set indicates that the PLL’s output
clocks have stopped following the selected reference
because the frequency offset of the selected refer-
ence is out of pull-in range (OOP). User can write to
the Control Mode register to program whether the
PLL shall follow the selected reference outside of the
specified pull-in range or just stay within the pull-in
range boundary.
FEE bit
This bit indicates whether an error occurs in the frame
edge detection process in frame phase align mode.
DHT bit
This bit indicates whether the device holdover history
is tracking on the current selected reference (updat-
ing by the short-term history).
HHA bit
This bit indicates the availability of the device hold-
over history.
External SYNC Input and Reference
Inputs Details
The STC5415 accepts 5 external reference inputs.
The reference inputs may be selected to accept either
the auto-detect acceptable reference frequency which
can be automatically detected or manually acceptable
reference frequency. Reference inputs REF4 and
REF5 are LVPECL/LVDS/LVCMOS and the remain-
ing three are LVCMOS. All 5 reference inputs are
monitored continuously for frequency, activity and
quality. The timing generator may select any of the
reference inputs when the device is in external timing
mode.
External Frame Sync Inputs
The STC5415 has an external frame sync input at
2kHz or 8kHz on the pin EX_SYNC. The frequency of
the external frame sync input is auto-detected.
To achieve frame alignment, input EX_SYNC may be
selected as frame rFeufenrecntcioe nfoarl SsepleeccteifdicRaEtiFo1nto
REF5 individually at the register Frame Phase Align.
Sampling edge of the external sync inputs can be
configured as falling or rising at the register EX SYNC
Edge Config. If an error occurs when sampled on the
selected frame edge of the selected reference, bit
FEE of the register PLL Status will be asserted and
the frame pulse clock output CLK8K will replace the
selected frame reference input as the temporary
frame reference. The error does not impact bit SYNC
and LOL of the register PLL Status. User can invoke
a re-lock event to PLL by programming the register
PLL Event In. The frame edge is re-selected as well.
Acceptable Frequency and Frequency Offset
Detection
The STC5415 can automatically detect the frequency
of the reference input when the user enable the auto-
detection function at the register Ref Freq. The
acceptable auto-detect frequencies are: 8kHz, 64kHz,
1.544MHz, 2.048MHz, 19.44MHz, 38.88MHz,
77.76MHz, 6.48MHz, 8.192MHz, 16.384MHz,
25MHz, 50MHz or 125MHz. These frequencies can
be detected automatically in the detector. The detec-
tor operates continuously to detect the frequency of
reference inputs. Any carrier frequency change will be
detected within 1ms. Each input is also monitored for
frequency offset between input and the internal fre-
erun clock. The frequency offset is a key factor to
determine qualification of the reference inputs. See
register Ref Index Selector and Ref Info.
STC5415 provides another option which allows the
user to select the manually acceptable reference fre-
quency for all the reference inputs, at the integer mul-
tiple of 8kHz (Nx8kHz, N is integer from 1 to 32767).
Hence the manually acceptable reference frequency
range is integer multiple of 8kHz from 8kHz to
262.136MHz. When a manually acceptable reference
frequency is used, the user need to access the regis-
ter Ref Freq to set the integer N. Each input is moni-
tored for frequency offset between input and the
internal freerun clock. The frequency offset is shown
in the register Ref Info when associate reference
index is selected at the register Ref Index Selector.
Activity Monitoring
Activity monitoring is also a continuous process which
is used to identify if the reference input is in normal. It
is accomplished with a leaky bucket accumulation
algorithm, as shown in Figure 2. The “leaky bucket”
Preliminary
Page 18 of 48 TM120 Rev: P1.3
Date: September 20, 2011
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice