STC5415 Datasheet, PDF (1/48 Pages) Connor-Winfield Corporation – Line Card Clock

STC5415
Line Card Clock
Data sheet
Description
Features
Functional Specification
The RoHS 6/6 compliant STC5415 is a single chip
clock synchronization solution for line card applica-
tions in SDH, SONET, and Synchronous Ethernet
network elements.
The STC5415 accepts 5 clock reference inputs, 1
external frame sync input EX_SYNC, and generates
4 synchronized clock outputs. Synchronized outputs
may be programmed for wide variety of frequencies
from 1MHz up to 156.25MHz, in 1kHz steps. Refer-
ence inputs are individually monitored for activity and
quality. Reference selection may be automatic, man-
ual, or hard-wired manual.
The timing generator may operate in the Freerun,
Synchronized, and Holdover mode. It includes a
DSP-based PLL. Synchronized mode is external tim-
ing while freerun and holdover mode are self-timing.
DSP-based PLL technology removes any external
component except the oscillator. It provides excellent
performance and reliability to STC5415.
The STC5415 is clocked by an external oscillator,
either a stable TCXO or XO, as required by applica-
tion.
- Suitable for SONET, SDH, Synchronous Ethernet appli-
cations
- Supports 4 different frequencies of external oscillator
upon soft-reset: 10MHz, 12.8MHz, 19.2MHz, 20MHz
- Provides one 2kHz or 8kHz external frame sync input
- Accepts 5 clock reference inputs
- Supports automatically frequency detection or manually
acceptable frequency. Each reference input is monitored
for activity and quality
- Automatic, manual, and hard-wired manual reference
selection
- Outputs 4 synchronized clock outputs, including 2 frame
pulse clocks
- Frequency translation of input clock to a different local
line card clock
- 3 clock synthesizers generate frequencies
- Phase-align locking or hit-less reference switching
- Programmable loop bandwidth, from 13Hz to 100Hz
- Programmable phase skew in synthesizer level
- SPI bus interface
- Single 3.3V operation
- Available in TQFP64 package
SRCSW
EX_SYNC
Timing
Generator
Synth
F
8kHz
2kHz
Synthesizer G₁
Ref Clk
5
3 LVCMOS
+
2 LVPECL/LVDS/LVCMOS
Ref
Monitor
Synthesizer G₄
TCXO
XO
SPI Interface
Figure 1:Functional Block Diagram
CLK8K
CLK2K
CLK1, LVPECL/LVDS
CLK2
Preliminary
Page 1 of 48 TM120 Rev: P1.3
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 20, 2011