FX929A Datasheet, PDF (36/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX929A
It is also possible to use the modem in a non-standard system where there is an indeterminate delay between
the transmitter start-up and the Symbol Sync pattern, or where a receive carrier detect signal is not available to
the controlling µC, or where the transmitting terminal can send separate unsynchronised Frames. In these
cases each Frame should be preceded by a Symbol Sync pattern which should be extended to about 100
symbols, and the procedure given in paragraphs (1) to (4) above used at all times.
Setting the AQSC and AQLEV bits to '1' triggers the modem's automatic Symbol Clock Extraction and Level
Measurement acquisition sequences, which are designed to measure the received symbol timing, amplitude
and dc offset as quickly as possible before switching to more accurate - but slower - measurement modes.
These acquisition sequences act very quickly if triggered at the start of a received Symbol Sync pattern (as
shown in Figure 17), but will still function correctly - although more slowly - if started any time during a normal
Frame, as when the receiver is switched onto a channel where the transmitter is operating continuously.
The automatic AQLEV Level Measurement acquisition sequence starts with the level measurement circuits
being put into 'Clamp' mode for one symbol time to set the voltages on the DOC pins to some point within the
range of the received signal excursions. The level measurement circuits are then automatically set to 'Lossy
Peak Detect' mode for 15 symbol times, after which the sequence ends and the level measurement circuit
modes reverts to the mode set by the LEVRES bits of the Control Register (normally 'Slow Peak Detect').
The peak detectors used in both 'Slow' and 'Lossy Peak Detect' modes include additional low pass filtering of
the received signal which greatly reduces the effect of pattern noise on the reference voltages held on the
external DOC capacitors, but means that pairs of '+3' (and '-3') symbols need to be received to establish the
correct levels. 2 pairs of '+3' and two pairs of '-3' symbols received after the start of an AQLEV sequence are
sufficient to set the levels on the DOC capacitors to their optimum levels.
The automatic AQSC Symbol Clock acquisition sequence sets the PLL to 'Extra Wide Bandwidth' mode for 16
symbol times (this mode is not one of those which can be selected by the Control Register PLLBW bits) then
changes to 'Wide' bandwidth. After 45 symbol times the PLL mode will revert to that set by the Control Register
PLLBW bits.
1.6.4 AC Coupling
For a practical circuit, ac coupling from the modem's transmit output to the frequency modulator and between
the receiver's frequency discriminator and the receive input of the modem may be desired. There are, however,
two problems:
Firstly, ac coupling of the signal degrades the Bit Error Rate performance of the modem. The following graph
illustrates the typical bit error rates at 4800 symbols/sec (without FEC) for differing degrees of ac coupling:
© 1996 Consumer Microcircuits Limited
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D/929A/4